LM3S102-IRN20 Luminary Micro, Inc., LM3S102-IRN20 Datasheet - Page 273
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LM3S102-IRN20
Manufacturer Part Number
LM3S102-IRN20
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
1.LM3S102-IRN20.pdf
(335 pages)
- Current page: 273 of 335
- Download datasheet (2Mb)
13.3
13.4
October 6, 2006
Table 13-1 gives examples of Timer period, system clock, and speed mode (Standard or Fast).
Table 13-1. Examples of I
Initialization and Configuration
The following example shows how to configure the I
This assumes the system clock is 20 MHz.
1.
2.
3.
4.
5.
6.
7.
8.
Register Map
Table 13-2 lists the I
master and slave:
12.5 Mhz
16.7 Mhz
System
20 Mhz
Clock
4 Mhz
6 Mhz
Enable the I
Control module.
In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation.
Initialize the I
Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPR register represents the number of system clock
periods in one SCL clock period. The TPR value is determined by the following equation:
TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1;
TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1;
TPR = 9
Write the I2CMTPR register with the value of 0x00000009.
Specify the slave address of the master and that the next operation will be a Send by writing
the I2CMSA register with a value of 0x00000076. This sets the slave address to 0x3B.
Place data (byte) to be sent in the data register by writing the I2CMDR register with the
desired data.
Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with
a value of 0x00000007 (STOP, START, RUN).
Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has
been cleared.
I
2
C Master: 0x40020000
Period
2
Timer
0x01
0x02
0x06
0x08
0x09
C clock by writing a value of 0x00001000 to the RCGC1 register in the System
2
C Master by writing the I2CMCR register with a value of 0x00000020.
2
C registers. All addresses given are relative to the I
2
Standard
100 Kbps
100 Kbps
100 Kbps
89 Kbps
93 Kbps
C Master Timer Period versus Speed Mode
Mode
Preliminary
Period
Timer
0x01
0x02
0x02
-
-
2
C module to send a single byte as a master.
312 Kbps
278 Kbps
333 Kbps
Mode
Fast
-
-
2
C base addresses for the
LM3S102 Data Sheet
273
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