LM3S102-IRN20 Luminary Micro, Inc., LM3S102-IRN20 Datasheet - Page 102
![no-image](/images/no-image-200.jpg)
LM3S102-IRN20
Manufacturer Part Number
LM3S102-IRN20
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
1.LM3S102-IRN20.pdf
(335 pages)
- Current page: 102 of 335
- Download datasheet (2Mb)
General-Purpose Input/Outputs (GPIOs)
Figure 8-2. GPIO Port Block Diagram
8.2.1
102
Alternate Input
Alternate Output
Alternate Output Enable
Interrupt
Data Register Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 108) by using bits [9:2] of the address bus as a mask.
This allows software drivers to modify individual GPIO pins in a single instruction, without affecting
the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write
operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA
register covers 256 locations in the memory map.
During a write, if the address bit associated with that data bit is set to 1, the value of the
GPIODATA register is altered. If it is cleared to 0, it is left unchanged.
For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in
Figure 8-3, where u is data unchanged by the write.
GPIOAFSEL
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIODATA
Selection
GPIOMIS
Function
GPIODIR
Interrupt
GPIOIBE
GPIOIEV
GPIORIS
GPIOICR
GPIOIM
Control
GPIOIS
Data
I/O
Identification Registers
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIO Input
GPIO Output
GPIO Output Enable
GPIODR2R
GPIODR4R
GPIODR8R
GPIOODR
GPIOPUR
GPIOPDR
GPIODEN
GPIOSLR
Control
I/O Pad
GPIOPCellID1
GPIOPCellID3
GPIOPCellID0
GPIOPCellID2
D
E
M
U
X
M
U
X
M
U
X
Preliminary
Pad Input
Pad Output
Pad Output Enable
Pad
I/O
October 6, 2006
Package I/O Pin
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