MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 79

• Manufacturer Part Number: MT90883
• Description: (MT90880 - MT90883) TDM to Packet Processors
• Manufacturer: Zarlink Semiconductor

Free-run Mode is typically used when a master clock source is required, or immediately following system
power-up before network synchronization is achieved.
6.13.4
Table 30 lists the key performance parameters of the DPLL.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
7.0
Details of the memory map and register definitions are included in the document "MT90880 Programmers'
Model" (related document 1).
8.0
8.1
Whenever the MT9088x device receives Ethernet packets which are corrupted (CRC error, too short or too long
etc.) the context related to the error packet will have incorrect data. The next valid packet following the error packet
will be lost and this may belong to a different context.
Intrinsic jitter
Lock range
Lock time
Free-run frequency accuracy
Master Mode Parameters (the following parameters are only applicable in master mode):
Phase slope output
Holdover frequency accuracy
MTIE during a reference switch
Slave Mode Parameters (the following parameters are only applicable in slave mode):
Input clock jitter tolerance (above 10 KHz)
Issue
Special Note to Users: MT9088x handling of received corrupted Ethernet packets
and dealing with the next valid packet
Memory Map and Register definitions
For the DPLL, the intrinsic output jitter is determined by the frequency of the master clock input (S_CLK). The edges of the
DPLL output clocks are synchronous to both edges of the master clock, giving a resolution of 7.6 ns for a 66 MHz clock. In
addition, any jitter present on the master clock is transferred without attenuation to the output clocks.
Note that the locking range is related to the master clock frequency (S_CLK). For example, if the master clock is -100 ppm,
the whole locking range also shifts -100 ppm downwards from -345ppm to 145ppm.
Assumes ideal master clock (S_CLK) frequency of 66.0 MHz. Any deviation of master clock frequency from 66 MHz directly
translates into a degradation of free-run frequency accuracy.
slope may not exceed 81 ns/1.327 ms (61 ppm).
translate directly into a holdover frequency error.
Maximum jitter is 1 UI (1 bit period) of input clock frequency. With input clock frequencies of 2.048 MHz and 4.096 MHz, this
comfortably exceeds ITU-T standards G.823 and G.824 (references 11 and 12). With a 16.384 MHz input clock, this translates
to 61 ns, or 0.125 UI at 2.048 MHz. This is just outside the G.823 specification of 0.2 UI.
This is equivalent to 7ns per 125 µ s, or better than specified in GR-1244-CORE (reference 10) which states that the phase
Assumes no drift on the master clock (S_CLK) frequency. Any drift in master clock frequency after holdover is entered will
DPLL Performance Parameters
Parameter
Table 30 - DPLL Performance Parameters
Zarlink Semiconductor Inc.
MT90880/1/2/3
Min
79
± 0.005
± 245
± 0.06
± 3.8
Max
50
56
20
1
Units
ppm
ppm
ppm
ppm
ns
ns
UI
s
Note 1
Note 2
Note 3
Note 4
Note 5
Note 6
Comment
Data Sheet