MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 74

• Manufacturer Part Number: MT90883
• Description: (MT90880 - MT90883) TDM to Packet Processors
• Manufacturer: Zarlink Semiconductor

Queue Priority
While the CPU queues have no inherent priority levels associated with them, in that the CPU can choose to
service which queue it wants to first, there is a priority level associated with the DMA transfer into system
memory. The MT90880 uses a prioritised round robin methodology to determine which queue gets serviced
first, with L2P queue 3 having the highest priority and L2P queue 0 the lowest priority. Therefore the DMA will
only transfer packets in a given queue if all the higher priority queues are empty.
However, this is only true if there is room in the corresponding data structure in system memory for the DMA to
transfer into. If there are no empty data buffers for a particular queue then that queue will be stalled, irrespective
of its priority. The DMA engine will then continue to service the lower priority queues. Therefore the CPU can
also control the priority by how fast it processes each queue.
6.12
6.12.1
The JTAG port is used to access the boundary scan logic for board level production testing. A NAND tree test
mode is also provided on the MT9088x family. The MT9088x JTAG interface conforms to the IEEE standard
1149.1 (reference 4, Table 2). This standard specifies a design-for-testability technique called "Boundary-Scan
Test" (BST). An external Test Access Port (TAP) Controller controls the operation of the boundary scan circuitry.
Details of the contents of the scan register are contained in the BSDL file.
Board Level Test Features
JTAG Support
MT90880
packets for a match and
Packet Classification
Search the incoming
appropriate queue
forward to the
Figure 35 - DMA Operation from CPU Packet Queues
Zarlink Semiconductor Inc.
MT90880/1/2/3
CPU queues
L2P queue 0
L2P queue 1
L2P queue 2
L2P queue 3
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Ring/List 0
Ring/List 1
Ring/List 2
Ring/List 3
Descriptor lists in
System Memory
Data Sheet