MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 18

• Manufacturer Part Number: MT90883
• Description: (MT90880 - MT90883) TDM to Packet Processors
• Manufacturer: Zarlink Semiconductor

3.6
The system signals are 5 V tolerant.
RESOUT# is low while S_RST# is low.
The core of the chip will be held in reset for 16348 S_CLK cycles after S_RST# has gone high and 16348
PCI_CLK cycles after PCI_RST# have gone high to allow the PLLs to lock.
3.7
3.7.1
All JTAG signals are 5 V tolerant.
3.7.2
All test signals are 5 V tolerant except for IDDQ, SCLK_AT1 and PCLK_AT1.
s_clk
s_rst#
resout#
jtag_trst#
jtag_tck
jtag_tms
jtag_tdi
jtag_tdo
t_mode[1:0]
t_d[15:0]
Signal
Signal
System Control Interface
Test Facilities
Signal
JTAG Interface
Test Facility
IOU
O U
I/O
I/O
O
I/O
I
I
I
I
O
I
I
AF14 [1], AC14 [0]
AC15 [15], AE14 [14], AB15 [13], AD14 [12],
AF15 [11], AE15 [10], AD15 [9], AF16 [8],
AB16 [7], AE16 [6], AC17 [5], AD16 [4],
AF17 [3], AE17 [2], AD17 [1], AF18 [0]
AB17
AB18
AC18
AD18
AE18
B25
D24
C25
Table 10 - System Control Interface
Package Balls
Package Balls
Table 11 - JTAG Interface
Width
Zarlink Semiconductor Inc.
MT90880/1/2/3
18
JTAG reset. Must be pulled low
externally for normal operation.
JTAG test clock
JTAG test mode select
JTAG test data input
JTAG test data output
System clock
Reset input
Reset PHY
Test – Set Mode upon Reset
00 - PLL test mode
01 - Scan test mode
10 - Board level test mode
11 - Normal operation
Test MUX output.
Also used as bootstrap pins to
configure the device following a reset.
Description
Description
Description
Data Sheet