MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 68

• Manufacturer Part Number: MT90883
• Description: (MT90880 - MT90883) TDM to Packet Processors
• Manufacturer: Zarlink Semiconductor

This time must be reduced by transmission times of signals across the board between the MT90880 and the
memory, e.g. RAM_WE[x]# and the data bus, so in practice, the clock skew must be somewhat lower than this
figure suggests.
The read cycle (Figure 50) is not affected by clock skew in the same way. The MT90880 puts out an output
enable, RAM_OE[x]#, a time T
response time (T
the output enable and data setup are timed to the clock at the MT90880, board level clock skew does not
influence the read cycle timing.
Therefore the maximum allowable RAM output valid time T
For a 7.5 ns speed grade MT58L256L32P, the RAM output valid time T
required time with 0.45 ns to spare, although as before, some allowances should also be made for transmission
time of the control and data signals across the board.
6.10
This is a full master/target capable PCI bus interface capable of operation at 33 MHz. Since it has a data width
of 32 bits, this can provide up to 1 Gbit/s of data transfer. The PCI interface can be used by an external CPU to
provide full access to on-chip registers, and both on-chip memory and the main off-chip packet memory, via the
memory management unit. It also contains a DMA controller, which can be used to automatically transfer data
between off-chip packet memory and system memory on the PCI bus.
The PCI Core is fully compliant with the PCI Rev 2.2 Specification (reference 2, Table 2) provided by the PCI
Special Interest Group (PCI-SIG) responsible for global PCI Standards. Note that signals pci_serr# and
pci_inta# are not open drain, and require external circuitry so that the board itself, on which the MT9088x is
used, is PCI compliant. See “Open Drain Circuitry” on page 71.
Features include:
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6.10.1
The MT9088x family PCI interface only supports 32-bit PCI addressing and 32-bit wide PCI data transactions. If
an 8 or 16 bit data transaction is attempted, the MT9088x responds as though the transaction is 32 bits wide.
Hence an 8 or 16 bit read will result in the full 32 bits being placed on the PCI databus, and an 8 or 16 bit write
will result in the full 32 bits on the data bus being written into the register or memory location.
The MT9088x requires the master to break 64 bit transactions into two 32 bit accesses, in accordance with the
PCI revision 2.2 specification (section 3.2.3).
PCI revision 2.2 compliant
33 MHz operation
32 bit wide data bus
Master/Target capable
Scatter/gather DMA controller, capable of following down a linked list of packets for transfer
Allows target access to all on-chip registers and memory, and to external packet memory
Maximum allowable clock skew
Max. allowable RAM output valid time = T
PCI Interface
Address and Data Width support
OEQ
), and this data has to meet a setup time T
RAV
after S_CLK. In response, the RAM puts the data out onto the bus within a
= 15.15 - 10 - 1.5
= 3.65 ns
= 15.15 - 7.5 - 3
= 4.65 ns
Zarlink Semiconductor Inc.
MT90880/1/2/3
S_CLK
- T
68
RAV
OEQ
- T
RDS
RDS
is determined by the equation:
to S_CLK back at the MT90880. Since both
OEQ
is 4.2 ns. This part therefore meets the
Data Sheet