MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 46

• Manufacturer Part Number: MT90883
• Description: (MT90880 - MT90883) TDM to Packet Processors
• Manufacturer: Zarlink Semiconductor

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6.2.1
Although the switch unit itself is non-blocking, care must be taken with the multiplexing arrangement, since it is
possible to set up a blocking configuration outside of the switch. This is because there are two paths at each
multiplexer, so when one path has been used for a given timeslot, the other path is blocked. It is also possible to
block the output from the switch to a given output timeslot on the WAN side of the switch.
For example, consider the following flow from WAN Access Interface to the Packet Interface, re-ordering using
the switch. The input to the WAN Access Interface at stream 0 channel 0 enters the switch, and is re-mapped
onto stream 1 channel 0 before entering the WAN Receive block.
This ties up the following resources:
Similar considerations apply to other routes through the device. In general, restricting the use of re-ordering to use
either on input to or output from the device reduces the potential for blocking. Similarly, loopback from WAN to WAN
also sets up significant blocking potential (two muxes and the switch output), and should be avoided in normal
operation where possible.
6.2.2
One application of the TDM switch is to re-order channels either on the input or output of the device. This may
sometimes be necessary to provide a completely flexible channel mapping, since the packet
assembly/disassembly process cannot vary the order of channels within a context. Hence a channel arriving at
the packet assembly before another will always exit the packet disassembly process at the receiving end before
the second channel. Where it is required to map the channels differently, the TDM switch can be used to handle
the re-ordering.
For example, consider the following channel mappings:
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Although individually channels can be mapped to any other channel at the packet receive end, if both these
channels are contained in the same context, the packet assembly/disassembly process cannot provide this
mapping, since the order of channels is changed.
Therefore there are three options to obtain the desired mapping:
1. use two separate contexts for the two channels
2. re-order the channels on input using the switch
3. re-order the channels on output using the switch
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Per-channel high impedance output control for local and WAN streams
Per-channel message mode for local and WAN output streams
PRBS pattern generation and testing
Block memory programming for fast device initialisation
Channel duplication facility for broadcast and conference applications
Stream 0, channel 0 is mapped to stream 0, channel 1
Stream 0, channel 1 is mapped to stream 0, channel 0
Switch input mux. at stream 0, channel 0
WAN Receive input mux. at stream 1,
channel 0
Switch output for stream 1, channel 0
Multiplexing and Blocking
Re-ordering Timeslots
Zarlink Semiconductor Inc.
MT90880/1/2/3
prevents the WAN transmit output on stream 0, channel 0
being routed via the switch (e.g., for re-ordering or directing to
the Local interface.
prevents the direct connection of WAN Access Interface
stream 1, channel 0 to WAN Receive block.
prevents any connection from the Local interface to stream 1,
channel 0 on the WAN Access Interface.
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Data Sheet