MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 30

• Manufacturer Part Number: MT90883
• Description: (MT90880 - MT90883) TDM to Packet Processors
• Manufacturer: Zarlink Semiconductor

packets. Once confirmation has been received, the changes are activated at the transmit end. A
synchronization flag in the header marks the first modified packet. This tells the receiver to switch over to the
amended context information.
Removal of a context is signalled in the same way, with an acknowledgement from the receiver. Following
“tear-down”, the internal queues are cleared, and any packets received for that context are discarded.
5.3
The major data flows within the device are as follows:
1. WAN Access Interface to Packet Interface
2. Packet Interface to WAN Access Interface
3. WAN Access Interface to Packet Interface via a Local Resource Pool
4. Packet Interface to WAN Access Interface via a Local Resource Pool
5. PCI Interface to Packet Interface
6. Packet Interface to PCI Interface
WAN Access Interface to Packet Interface
Data traffic received on the WAN interface is divided into packets by the WAN Receiver. The packets are stored
in the external packet memory. A pointer to the packet is passed to the queue manager, which appends
completed packets to the appropriate transmission queue. On transmission the packet is retrieved from memory
by the Packet Formatter, a pre-defined header added, and then passed to the MAC for transmission.
Data and Control Flows
Figure 11 - WAN to Packet Data and Control Flow
Local TDM
Interface
Zarlink Semiconductor Inc.
MT90880/1/2/3
Packet Memory
Host Interface
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Data Flow
Control Flow
Data Sheet