MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 72

• Manufacturer Part Number: MT90883
• Description: (MT90880 - MT90883) TDM to Packet Processors
• Manufacturer: Zarlink Semiconductor

6.11.1
Data for transfer to and from the MT90880 is held in a Descriptor Ring or List data structure in system memory
(see Figure 33 and Figure 34). Once the CPU has set up the descriptor structure, the DMA engine is simply told
where to find the head descriptor. The DMA engine co-ordinates the transfer of packets to and from the data
structures with minimal further CPU intervention.
The "ring" data structure (Figure 33) allows a circular buffer to be created. Once the descriptors have been set
up, they should never need re-programming, save to change the relevant status and command bits. The ring
data structure is useful when a finite size buffer is allocated for packet transfer.
A list structure (Figure 34) may also be used. This is similar to the ring, but final link pointer does not point back
to the head descriptor. This is useful where a more elastic buffer is required, but requires more CPU
intervention, since once the list has completed, it is necessary to re-program the DMA to point to the next set of
descriptors.
DMA Descriptor Rings and Lists
Head Descriptor
Buffer Pointer
Data Buffer
Command
Status
Link
Figure 33 - Descriptor Ring Structure
Buffer Pointer
Data Buffer
Command
Status
Link
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MT90880/1/2/3
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Buffer Pointer
Data Buffer
Command
Status
Link
Buffer Pointer
Data Buffer
Command
Status
Link
Data Sheet