MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 41

• Manufacturer Part Number: MT90883
• Description: (MT90880 - MT90883) TDM to Packet Processors
• Manufacturer: Zarlink Semiconductor

MT90880/1/2/3
Data Sheet
6.1.2
Operational Modes
The WAN Interface operates in three distinct modes: synchronous master , synchronous slave and
asynchronous mode.
Synchronous Master Mode
In synchronous master mode , the MT9088x supplies the clock and frame signals to the external WAN
infrastructure (e.g. framers or TDM backplane). The internal Stratum 4E DPLL is used to lock onto a primary
reference signal. This can be chosen from any one of the 32 incoming frame references. A secondary reference
may also be selected, and this is automatically switched in if the primary reference fails. The clock and frame
pulse generated by the DPLL are used as the master timing source to the WAN Access Interface, and to clock
in and out data on all 32 ports.
Typically, this configuration will be used to connect to framers. The MT9088x can be set to choose a primary
and secondary frame reference from any of the 32 ports. The internal DPLL is used to lock onto the chosen
reference, and provide a stable, low-jitter master clock to drive the TDM data buses between the framers and
the MT9088x device.
An example of this is shown in Figure 20. An MT90880 is shown connected to up to 32 MT9076 T1/E1
framer/LIU devices, using the ST-bus at 2.048 Mbs. Each framer generates a frame pulse when a frame
boundary is detected on the line, and this is fed into the MT90880 via the WAN interface's frame inputs
WAN_FRMI[x]. One of these is selected as a reference for the internal DPLL, which generates the 4.096 MHz
clock and the frame pulse required for the ST-bus operation. This is used both to clock data in and out of both
the framer and the MT90880. The clki[31:0] inputs should be left unconnected, as shown in the figure below.
41
Zarlink Semiconductor Inc.