MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 76

• Manufacturer Part Number: MT90883
• Description: (MT90880 - MT90883) TDM to Packet Processors
• Manufacturer: Zarlink Semiconductor

6.13
The MT9088x contains an internal Digital Phase Locked Loop (DPLL) which exceeds the requirements of
Stratum 4E. This is provided both to synchronise to external references and generate the internal clocks
required by the device when operating in synchronous mode.
The DPLL accepts two references, primary and secondary, selected from the incoming ports on the WAN
Access Interface. Failure of a reference is automatically detected, and the DPLL can switch between references
without introducing bit errors. Reference switching can be performed under automatic or manual control.
The DPLL operates in two main modes, "Master" and "Slave". In Master mode, the DPLL accepts an incoming
8KHz frame reference, and generates a stable, low jitter clock and frame pulse for the selected data format.
Master mode is generally used where the MT9088x is supplying the clocks to the TDM infrastructure, for
example, T1/E1 framers, or a TDM backplane such as H.110 or H-MVIP.
In
DPLL. The DPLL locks to both the clock and the frame pulse, and generates the internal clocking for the device.
This mode is used where the master clock and frame references are provided externally.
Features include:
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6.13.1
In master mode, the DPLL locks to an incoming 8KHz frame reference. It generates the clock and frame pulses
required by the selected data format on the WAN Access Interface (see Table 7 on page 16). From a device
reset condition or after a reference switch, the DPLL will take up to 50 seconds to phase lock the output signals
to the selected input reference signal.
Primary and Secondary References
The DPLL can operate with two references, a primary and a secondary, selected from any of input frame
references. The health of both selected references is continuously monitored. When an incoming reference
fails, the DPLL can either automatically switch to the alternate reference, or enter holdover operation. The
reference switch can then be manually controlled. Should the failed reference return, the device will re-lock to
the reference. The DPLL provides bit error free reference switching, meeting the phase slope and MTIE
requirements defined by the Telcordia GR-1244-CORE standard (reference 10, Table 3).
Holdover Operation
In Holdover, the DPLL maintains the clock frequency at the value recorded before the reference was judged to
have failed. Holdover is typically used for short durations while network synchronization is temporarily
disrupted. The initial accuracy of the held frequency is ± 0.06 ppm, which translates in the worst case to 42
frame (125 µ s) slips in 24 hours.
Slave mode, both the incoming and outgoing streams are timed using the external reference, bypassing the
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Telcordia GR-1244-CORE (reference 10, Table 3)
Exceeds Stratum 4E standard
Three fundamental modes of operation:
Primary and secondary references
Automatic detection of reference failure
Holdover operation, maintaining last locked reference frequency
Error-free reference switching, meeting
"Master" clock-generator mode - locks to incoming 8KHz frame reference
"Slave" clock-follower mode - locks to incoming clock and frame reference
"Free-run" mode allows clock generation without an external reference
DPLL Specification
Master Mode
Zarlink Semiconductor Inc.
MT90880/1/2/3
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Data Sheet