MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 75

• Manufacturer Part Number: MT90883
• Description: (MT90880 - MT90883) TDM to Packet Processors
• Manufacturer: Zarlink Semiconductor

6.12.2
The Test Access Port (TAP) accesses the MT9088x test functions. It consists of four input pins and one output
pin as follows:
Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remains
independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrently
with the operation of the device and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The TAP Controller uses the logic signals received at the TMS input to control test operations. The TMS signals
are sampled at the rising edge of the TCK pulse. This pin is internally pulled to V
external source.
Test Data Input (TDI)
Serial input data applied to this interface is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent
section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to V
when it is not driven from an external source.
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction register
or data register are serially shifted out towards the TDO. The data out of the TDO is clocked on the falling edge
of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is set to a high
impedance state.
Test Reset (TRST)
Reset the JTAG scan structure. This pin is internally pulled to VDD.
6.12.3
Instruction Register
The MT9088x uses the public instructions defined in the IEEE 1149.1 standard. The JTAG Interface contains a
two-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the
TAP Controller is in its shifted-IR state. These instructions are subsequently de-coded to achieve two basic
functions: to select the test data register that may operate while the instruction is current; and, to define the
serial test data register path that is used to shift data between TDI and DO during data register scanning.
Test Data Register
As specified in IEEE 1149.1, the MT9088x JTAG Interface contains three test data registers:
Boundary-Scan Register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around
the boundary of the MT9088x core logic.
Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path from TDI to its TDO.
Device Identification Register
The device identification register is a 32-bit register. The register contents are included in the BSDL file for the
chip.
Test Access Port (TAP)
Test Access Registers
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MT90880/1/2/3
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when it is not driven from an
Data Sheet
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