MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 78

• Manufacturer Part Number: MT90883
• Description: (MT90880 - MT90883) TDM to Packet Processors
• Manufacturer: Zarlink Semiconductor

All outputs are derived from the same signal, therefore these diagrams apply to all outputs. Using the method
mentioned above, the jitter attenuation can be calculated for all combinations of inputs and outputs.
Frame alignment
When operating in master mode, the incoming frame reference is used solely as a frequency reference. There
is no requirement on the width of the frame pulse. The output frame pulse must therefore be used as the master
for the devices connected to the MT9088x's WAN Access Interface. There is no guaranteed phase relationship
between the input frame pulse and the output master frame pulse.
6.13.2
Slave mode is used where the master clock and frame references are provided externally. Both the incoming
and outgoing streams are timed using the external reference, bypassing the DPLL. The DPLL locks to the
incoming clock and frame pulse, and is used solely to generate the internal clocks required by the device.
The input frequency combinations and frame pulse widths for correct slave mode operation are given in Table 7
on page 16. These correspond to the data formats selected for the WAN Access Interface.
When operating in slave mode, the MT9088x is capable of accepting timing references with jitter meeting ITU-T
standards G.823 and G.824 when operating in either Generic E1 or ST-Bus formats at 2.048 Mbs. When
operating in ST-bus format at 8.192 Mbs, the maximum allowable input jitter above 10 KHz is 61 ns (1 UI at the
input clock rate of 16.384 MHz). This translates to 0.125 UI at 2.048 MHz, or just outside the G.824 specification
of 0.2 UI.
6.13.3
In the Free-run Mode, the DPLL provides timing and synchronization signals, which are based on the frequency
of the master clock (S_CLK) only, and are not synchronized to a reference input. The DPLL outputs have a
frequency accuracy of ± 0.005 ppm plus the accuracy of the master clock. For example, clock output C8OB will
have a frequency of 8.192 MHz ± S_CLK accuracy ± 0.005 ppm).
Slave Mode
Free-run Mode
Figure 37 - Detailed DPLL Jitter Transfer Function Diagram
Zarlink Semiconductor Inc.
MT90880/1/2/3
78
Data Sheet