MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 47

• Manufacturer Part Number: MT90883
• Description: (MT90880 - MT90883) TDM to Packet Processors
• Manufacturer: Zarlink Semiconductor

Use of a separate context may not be acceptable, since the number of contexts on the MT9088x family is
limited to 128. Therefore the only option is to use the switch to re-order the channels. As described above, it is
best to choose up front whether to re-order channels on the input or output side, to avoid potential blocking
conditions in the multiplexed paths.
It should also be noted that channels routed via the switch (e.g., for re-ordering) incur a three-frame delay for
the switch operation. This is not the case for channels routed directly (e.g., WAN Access Interface to WAN
Receive block), which incur no delay. This may be a consideration for applications where end to end latency is
an issue.
6.2.3
The switch can also be used to broadcast a single input channel to multiple output channels. This is achieved
by programming the connection memory to map multiple output channels to the same input channel.
Care must be taken when using this feature, since it does create blocking both within the switch itself, and
through the multiplexing arrangement. This is because the number of available output channels is effectively
reduced, meaning that not all input channels to the switch will be able to be mapped to an output. Similarly, the
output multiplexer to the WAN Access Interface will be assigned to multiple broadcast channels, blocking those
channels for output paths from the WAN Transmit block.
6.3
The payload assembly process creates programmable length packet payloads from the TDM input streams. The
assembly process is extremely flexible; packets can contain any number of 64 Kbs timeslots. These channels
need not be contiguous, and in synchronous mode they can be selected from any input port. In asynchronous
mode each stream is independently clocked, which can result in phase and frequency differences between
streams. Therefore, in this mode payloads may only contain timeslots from a single port. Payloads may contain
any integer number of TDM frames. The structure of a packet is shown in Figure 18, “Packet Structure for
MT9088x Family,” on page 36.
Each stream of packets created by the packet assembler is known as a context. The packet assembler is
capable of handling up to 128 different contexts simultaneously. Each context is allocated an identifier that is
agreed in advance between the transmitting and receiving device, and this identifier is placed in each packet
header to indicate the contents of the packet.
Timeslots can be dynamically added to or deleted from a context. This helps to conserve bandwidth on the
packet network, by only transmitting the active timeslots. Context modifications must be indicated in advance to
the receiving end, and acknowledged before the change can be implemented, in order to allow the TDM data to
be correctly re-constructed.
At the receiving end of the packet network, the original TDM data must be re-constructed from the packets
received. This is known as re-formatting, and follows the reverse process. A programmable jitter buffer is
provided to iron out the packet delay variation across the network. The size of the jitter buffer can be
programmed in units of TDM frames (i.e., steps of 125 µ s).
Features include:
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Supports up to 128 simultaneous packet streams or “contexts”.
Each context can handle any combination of timeslots, from any TDM stream.
Supports dynamic addition and deletion of timeslots.
Maintains timeslot order and TDM frame within each context.
Supports circuit emulation of structured T1 or E1 services.
Programmable number of TDM frames per packet.
Supports payload sizes from 1 to 1500 bytes.
Allows a user-defined static header to be attached to each packet.
WAN Receive and Transmit Functions
Channel Broadcast
Zarlink Semiconductor Inc.
MT90880/1/2/3
47
Data Sheet