MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 32

• Manufacturer Part Number: MT90883
• Description: (MT90880 - MT90883) TDM to Packet Processors
• Manufacturer: Zarlink Semiconductor

WAN Access Interface to Packet Interface via a Local Resource Pool
Data traffic received on the WAN interface is diverted to the TDM switch and out of the local TDM interface for
processing in a local resource pool (e.g., a DSP or other data processing unit). The processed data can re-enter
the device in two ways. Where the data is still constant bit rate, it can re-enter the device through the local TDM
interface, and be routed by the TDM switch to the WAN Receive block for packetisation.
Alternatively, if the processed data has been converted to a variable bit rate or packet format, it can be moved
into the device as through the PCI bus using the DMA controller to automatically fetch packets from system
memory. The Queue manager appends the packets to the appropriate transmission queue. On transmission the
packet is retrieved from memory and passed to the MAC for transmission.
Packet Interface to WAN Access Interface via a Local Resource Pool
Incoming data is received by the MAC, and its destination address is checked. Packets intended for this device
are passed to the packet receive block for placing in external memory, while the header is classified to
determine the appropriate destination. A pointer to the packet is passed to the queue manager to be placed on
the correct queue as indicated by the classification result.
If the destination is the PCI interface, the DMA controller is used to write the packets directly into system
memory. After local processing, the data is re-directed to the WAN interface by going through the Local TDM
interface and the TDM switch.
Figure 13 - WAN to Packet Data Flow via Local Resource
Local Resource Pool
e.g. DSP pool
Zarlink Semiconductor Inc.
MT90880/1/2/3
Packet Memory
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Data Flow
Control Flow
Data Sheet