XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 97

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

7.1 Introduction
7.2 EEPROM Programmer’s Model
M68HC12B Family — Rev. 8.0
MOTOROLA
Data Sheet — M68HC12B Family
The MCU is electrically erasable, programmable read-only memory (EEPROM)
serves as a 768-byte non-volatile memory which can be used for frequently
accessed static data or as fast access program code.
The MCU’s EEPROM is arranged in a 16-bit configuration. The EEPROM array
may be read as either bytes, aligned words, or misaligned words. Access time is
one bus cycle for byte and aligned word access and two bus cycles for misaligned
word operations.
Programming is by byte or aligned word. Attempts to program or erase misaligned
words will fail. Only the lower byte will be latched and programmed or erased.
Programming and erasing of the user EEPROM can be done in all operating
modes.
Each EEPROM byte or aligned word must be erased before programming. The
EEPROM module supports byte, aligned word, row (32 bytes), or bulk erase, all
using the internal charge pump. Bulk erasure of odd and even rows is also possible
in test modes; the erased state is $FF. The EEPROM module has hardware
interlocks which protect stored data from corruption by accidentally enabling the
program/erase voltage. Programming voltage is derived from the internal V
supply with an internal charge pump. The EEPROM has a minimum program/erase
life of 10,000 cycles over the complete operating temperature range.
The EEPROM module consists of two separately addressable sections. The first is
a 4-byte memory mapped control register block used for control, testing, and
configuration of the EEPROM array. The second section is the EEPROM array
itself.
At reset, the 4-byte register section starts at address $00F0 and the EEPROM
array is located from addresses $0D00 to $0FFF (see
on remapping the register block and EEPROM address space, refer to
Operating Modes and Resource
EEPROM
Mapping.
Section 7. EEPROM
Figure
7-1). For information
Section 5.
Data Sheet
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