XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 192

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Enhanced Capture Timer (ECT) Module
13.4.15 16-Bit Modulus Down-Counter Flag Register
Data Sheet
192
FLMC — Force Load Register into the Modulus Counter Count Register Bit
MCEN — Modulus Down-Counter Enable Bit
MCPR1 and MCPR0 — Modulus Counter Prescaler Select Bits
Read: Anytime
Write: Only for clearing bit 7
MCZF — Modulus Counter Underflow Interrupt Flag
POLF3–POLF0 — First Input Capture Polarity Status Bits
This bit is active only when the modulus down-counter is enabled (MCEN = 1).
Writing a 1 into this bit loads the load register into the modulus counter count
register. This also resets the modulus counter prescaler. Writing 0 to this bit has
no effect.
When MODMC = 0, the counter starts counting and stops at $0000. Reads of
this bit will return always 0.
When MCEN = 0, the counter is preset to $FFFF. This will prevent an early
interrupt flag when the modulus down-counter is enabled.
These two bits specify the division rate of the modulus counter prescaler. The
newly selected prescaler division rate will not be effective until a load of the load
register into the modulus counter count register occurs.
The flag is set when the modulus down-counter reaches $0000. Writing 1 to this
bit clears the flag. Writing 0 has no effect. Any access to the MCCNT register
will clear the MCZF flag in this register when TFFCA bit in register TSCR ($86)
is set.
This are read-only bits. Writing to these bits has no effect. Each status bit gives
the polarity of the first edge which has caused an input capture to occur after
capture latch has been read. Each POLFx corresponds to a timer PORTx input.
Address: $00A7
Reset:
Figure 13-36. 16-Bit Modulus Down-Counter Flag Register (MCFLG)
Read:
Write:
0 = Modulus counter disabled.
1 = Modulus counter is enabled.
0 = The first input capture has been caused by a falling edge.
1 = The first input capture has been caused by a rising edge.
MCPR1
MCZF
Bit 7
0
0
1
1
Enhanced Capture Timer (ECT) Module
0
MCPR0
6
0
0
0
1
0
1
5
0
0
Division Rate
Prescalar
16
1
4
8
4
0
0
POLF3
3
0
POLF2
M68HC12B Family — Rev. 8.0
2
0
POLF1
1
0
MOTOROLA
POLF0
Bit 0
0