XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 329

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

18.4.2 Breakpoint Registers
18.4.2.1 Breakpoint Control Register 0
M68HC12B Family — Rev. 8.0
MOTOROLA
Breakpoint operation consists of comparing data in the breakpoint address
registers (BRKAH/BRKAL) to the address bus and comparing data in the
breakpoint data registers (BRKDH/BRKDL) to the data bus. The breakpoint data
registers also can be compared to the address bus. The scope of comparison can
be expanded by ignoring the least significant byte of address or data matches.
The scope of comparison can be limited to program data only by setting the BKPM
bit in breakpoint control register 0.
To trace program flow, setting the BKPM bit causes address comparison of
program data only. Control bits are also available that allow checking read/write
matches.
Read and write anytime.
This register is used to control the breakpoint logic.
BKEN1 and BKEN0 — Breakpoint Mode Enable Bits
BKPM — Break on Program Addresses
BKEN1
See
This bit controls whether the breakpoint causes an immediate data breakpoint
(next instruction boundary) or a delayed program breakpoint related to an
executable opcode. Data and unexecuted opcodes cannot cause a break if this
Address: $0020
0
0
1
1
Reset:
Read:
Write:
Table
BKEN0
BKEN1
Figure 18-10. Breakpoint Control Register 0 (BRKCT0)
Bit 7
0
1
0
1
0
18-7.
Breakpoints off
SWI — dual address
mode
BDM — full breakpoint
mode
BDM — dual address
mode
BKEN0
Development Support
Table 18-7. Breakpoint Mode Control
6
0
Mode Selected
BKPM
5
0
4
0
0
BRKAH/L
Address
Address
Address
Usage
match
match
match
BK1ALE
—
3
0
BK0ALE
BRKDH/L
Address
Address
Usage
match
match
match
2
0
Data
—
Development Support
1
0
0
R/W
Yes
Yes
No
—
Breakpoints
Data Sheet
Range
Bit 0
Yes
Yes
Yes
0
0
—
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