XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 199

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

13.4.26 Modulus Down-Counter Count Registers
M68HC12B Family — Rev. 8.0
MOTOROLA
Read: Anytime
Write: Anytime
These registers are used to latch the value of the corresponding pulse accumulator
when the related bits in register ICPACR ($A8) are enabled (see
Accumulators).
Read: Anytime
Write: Anytime
A full access for the counter register should take place in one clock cycle. A
separate read/write for high byte and low byte will give different results than
accessing them as a word. If the RDMCL bit in MCCTL register is cleared, reads
of the MCCNT register will return the present value of the count register. If the
RDMCL bit is set, reads of the MCCNT will return the contents of the load register.
If a $0000 is written into MCCNT and modulus counter while LATQ and BUFEN in
ICSYS ($AB) register are set, the input capture and pulse accumulator registers
will be latched. With a $0000 write to the MCCNT, the modulus counter will stay
at 0 and does not set the MCZF flag in MCFLG register.
If modulus mode is enabled (MODMC = 1), a write to this address will update the
load register with the value written to it. The count register will not be updated with
Address: $00B5
Address: $00B6
Address: $00B7
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Figure 13-49. 8-Bit Pulse Accumulator Holding Register 0 (PA0H)
Figure 13-50. Modulus Down-Counter Count Registers (MCCNT)
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Enhanced Capture Timer (ECT) Module
0
1
1
Bit 14
Bit 6
Bit 6
6
0
6
1
6
1
Bit 13
Bit 5
Bit 5
5
0
5
1
5
1
Bit 12
Bit 4
Bit 4
4
0
4
1
4
1
Enhanced Capture Timer (ECT) Module
Bit 11
Bit 3
Bit 3
3
0
3
1
3
1
Bit 10
Bit 2
Bit 2
2
0
2
1
2
1
13.3.2 Pulse
Bit 1
Bit 9
Bit 1
Timer Registers
1
0
1
1
1
1
Data Sheet
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
0
1
1
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