XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 138

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Pulse-Width Modulator (PWM)
11.2.3 PWM Enable Register
Data Sheet
138
Read: Anytime
Write: Anytime
Setting any of the PWENx bits causes the associated port P line to become an
output regardless of the state of the associated data direction register (DDRP) bit.
This does not change the state of the data direction bit. When PWENx returns to 0,
the data direction bit controls I/O direction. On the front end of the PWM channel,
the scaler clock is enabled to the PWM circuit by the PWENx enable bit being high.
When all four PWM channels are disabled, the prescaler counter shuts off to save
power. There is an edge-synchronizing gate circuit to guarantee that the clock is
only enabled or disabled at an edge.
PWEN3 — PWM Channel 3 Enable Bit
PWEN2 — PWM Channel 2 Enable Bit
PWEN1 — PWM Channel 1 Enable Bit
PWEN0 — PWM Channel 0 Enable Bit
The pulse modulated signal will be available at port P bit 3 when its clock source
begins its next cycle.
The pulse modulated signal will be available at port P bit 2 when its clock source
begins its next cycle.
The pulse modulated signal will be available at port P bit 1 when its clock source
begins its next cycle.
The pulse modulated signal will be available at port P bit 0 when its clock source
begins its next cycle.
Address: $0042
Reset:
Read:
Write:
0 = Channel 3 disabled
1 = Channel 3 enabled
0 = Channel 2 disabled
1 = Channel 2 enabled
0 = Channel 1 disabled
1 = Channel 1 enabled
0 = Channel 0 disabled
1 = Channel 0 enabled
Bit 7
0
0
Pulse-Width Modulator (PWM)
Figure 11-6. PWM Enable Register (PWEN)
= Unimplemented
6
0
0
5
0
0
4
0
0
PWEN3
3
0
PWEN2
M68HC12B Family — Rev. 8.0
2
0
PWEN1
1
0
MOTOROLA
PWEN0
Bit 0
0