XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 35

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

1.6.4.4 Port DLC
1.6.4.5 Port CAN
M68HC12B Family — Rev. 8.0
MOTOROLA
The PEAR register determines pin function, and the data direction register (DDRE)
determines whether each pin is an input or output when it is used for
general-purpose I/O. PEAR settings override DDRE settings. Because PE1 and
PE0 are input-only pins, only DDRE7–DDRE2 have effect. Setting a bit in the
DDRE register makes the corresponding bit in port E an output; clearing a bit in the
DDRE register makes the corresponding bit in port E an input. The default reset
state of DDRE is all 0s.
When the PUPE bit in the PUCR register is set, PE7, PE3, PE2, and PE0 are pulled
up. PE7, PE3, PE2, and PE0 are active pulled-up devices, while PE1 is always
pulled up by means of an internal resistor.
Port E and DDRE are not in the map in peripheral mode or in expanded modes
when the EME bit in the MODE register is set.
Setting the RDPE bit in register RDRIV causes all port E outputs to have reduced
drive level. RDRIV can be written once after reset. RDRIV is not in the address map
in peripheral mode. Refer to Section 6. Bus Control and Input/Output (I/O).
The MC68HC912B32 and MC68HC12BE32 contain the port DLC.
Byte data link communications (BDLC) pins can be configured as general-purpose
I/O port DLC. When BDLC functions are not enabled, the port has seven
general-purpose I/O pins, PDLC6–PDLC0. The port DLC control register
(DLCSCR) controls port DLC function. The BDLC function, enabled with the
BDLCEN bit, takes precedence over other port functions.
The port DLC data direction register (DDRDLC) determines whether each port DLC
pin is an input or output. Setting a bit in DDRDLC makes the corresponding pin in
port DLC an output; clearing a bit makes the corresponding pin an input. After
reset, port DLC pins are configured as inputs.
When the PUPDLC bit in the DLCSCR register is set, all port DLC input pins are
pulled up internally by an active pullup device.
Setting the RDPDLC bit in register DLCSCR causes all port DLC outputs to have
reduced drive level. Levels are at normal drive capability after reset. RDPDLC can
be written anytime after reset. Refer to
Communications
The MC68HC(9)12BC32 contains the port CAN.
The port CAN has five general-purpose I/O pins, PCAN[6:2]. The msCAN12
receive pin, RxCAN, and transmit pin, TxCAN, cannot be configured as
general-purpose I/O on port CAN.
(BDLC).
General Description
Section 15. Byte Data Link
Pinout and Signal Descriptions
General Description
Data Sheet
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