XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 323

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

18.3.5 BDM Instruction Register
18.3.5.1 Hardware Command
M68HC12B Family — Rev. 8.0
MOTOROLA
on the parallel bus. It is discussed here for two conditions: when a hardware
command is executed and when a firmware command is executed.
The instruction register can be read or written in all modes. The hardware clears
the instruction register if 512 E-clock cycles occur between falling edges from the
host.
This section describes the BDM instruction register under hardware command and
firmware command.
The bits in the BDM instruction register have the following meanings when a
hardware command is executed.
H/F — Hardware/Firmware Flag
DATA — Data Flag
R/W — Read/Write Flag
BKGND — Hardware Request to Enter Active Background Mode
W/B — Word/Byte Tansfer Flag
BD/U — BDM Map/User Map Flag
Indicates whether BDM registers and ROM are mapped to addresses $FF00 to
$FFFF in the standard 64-Kbyte address space. Used only by hardware
read/write commands.
Address: $FF00
Reset:
Read:
Write:
0 = Firmware instruction
1 = Hardware instruction
0 = No data
1 = Data included in command
0 = Write
1 = Read
0 = Not a hardware background command
1 = Hardware background command (INSTRUCTION = $90)
0 = Byte transfer
1 = Word transfer
0 = BDM resources not in map
1 = BDM resources in map
Figure 18-4. BDM Instruction Register (INSTRUCTION)
Bit 7
H/F
0
Development Support
DATA
6
0
R/W
5
0
BKGND
4
0
W/B
3
0
Background Debug Mode (BDM)
BD/U
2
0
Development Support
1
0
0
Data Sheet
Bit 0
0
0
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