XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 206
XC912BC32CFU8
Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
1.XC912BC32CFU8.pdf
(362 pages)
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Serial Interface
14.2.2 SCI Baud Rate Generation
14.2.3 SCI Register Descriptions
14.2.3.1 SCI Baud Rate Control Register
Data Sheet
206
The basis of the SCI baud rate generator is a 13-bit modulus counter. This counter
gives the generator the flexibility necessary to achieve a reasonable level of
independence from the CPU operating frequency and still be able to produce
standard baud rates with a minimal amount of error. The clock source for the
generator comes from the P clock.
Control and data registers for the SCI subsystem are described here. The memory
address indicated for each register is the default address that is in use after reset.
The entire 512-byte register block can be mapped to any 2-Kbyte boundary within
the standard 64-Kbyte address space.
Address:
Address:
Reset:
Reset:
Read:
Write:
Read:
Write:
SCI Baud Rate
$00C0
$00C1
Desired
Figure 14-3. SCI Baud Rate Control Register (SC0BDH)
Figure 14-4. SCI Baud Rate Control Register (SC0BDL)
14,400
19,200
38,400
1200
2400
4800
9600
110
300
600
BTST
SBR7
Bit 7
Bit 7
0
0
BSPL
SBR6
Table 14-1. Baud Rate Generation
Serial Interface
6
0
6
0
BRLD
SBR5
5
0
5
0
BR Divisor for
P = 4.0 MHz
2273
833
417
208
104
52
26
17
13
—
SBR12
SBR4
4
0
4
0
SBR11
SBR3
3
0
3
0
M68HC12B Family — Rev. 8.0
SBR10
SBR2
2
0
2
1
BR Divisor for
P = 8.0 MHz
4545
1667
833
417
208
104
52
35
26
13
SBR9
SBR1
1
0
1
0
MOTOROLA
SBR8
SBR0
Bit 0
Bit 0
0
0
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