XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 251

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

M68HC12B Family — Rev. 8.0
MOTOROLA
NOTE:
DLOOP — Digital Loopback Mode Bit
The DLOOP bit is a fault condition aid and should never be altered after the BDR
is loaded for transmission. Changing DLOOP during a transmission may cause
corrupted data to be transmitted onto the J1850 network.
Before going into digital loopback mode, the RXPOL bit in the BARD register must
be set so that the receive polarity is not expected to be inverted.
RX4XE — Receive 4X Enable Bit
first, then sets ALOOP which resets the BDLC state machine to a known state.
When the user clears ALOOP, to indicate the transceiver has been taken out of
loopback mode, the BDLC waits for an EOF symbol before attempting to
transmit. Most transceivers have the ALOOP feature available.
This bit determines the source to which the BDLC internal digital receive input
is connected and can be used to isolate bus fault conditions. If a fault condition
has been detected on the bus, this control bit allows the programmer to connect
the digital transmit output to the digital receive input. In this configuration, data
sent from the transmit buffer is reflected back into the receive buffer. If no faults
exist in the BDLC, the fault is in the physical interface block or elsewhere on the
J1850 bus. When the DLOOP bit is set, the BDLC is disengaged from the J1850
bus. Therefore, the BDLC does not receive an edge from the J1850 bus which
would normally cause a BSVR non-maskable wakeup interrupt.
This bit determines if the BDLC operates at normal transmit and receive speed
(10.4 Kbps) or receive only at 41.6 Kbps. This feature is useful for fast
downloading data into a J1850 node for diagnostic or factory programming.
1 = Input to the analog physical interface’s final drive stage is looped back to
0 = BDLC digital circuitry drives an output for the J1850 bus. After the bit is
1 = BDRxD is connected to BDTxD. The BDLC is in digital loopback mode.
0 = BDTxD is not connected to BDRxD. The BDLC is taken out of digital
1 = BDLC is put in 4X receive-only operation.
0 = BDLC transmits and receives at 10.4 Kbps. Reception of a BREAK
the BDLC receiver. The J1850 bus is not driven.
cleared, the BDLC requires the bus to be idle for a minimum of
end-of-frame symbol time (t
minimum of inter-frame symbol time (t
transmission.
loopback mode and can now drive or receive the J1850 bus normally
(given ALOOP is not set). After clearing DLOOP, the BDLC requires the
bus to be idle for a minimum of end-of-frame symbol (t
allowing reception of a message. The BDLC requires the bus to be idle
for a minimum of inter-frame separator symbol (t
a message to be transmitted.
symbol automatically clears this bit and sets BDLC state vector register
(BSVR) to $001C.
Byte Data Link Communications (BDLC)
TRV4
) before message reception or a
Byte Data Link Communications (BDLC)
TRV6
) before message
tv6
) time before allowing
tv4
BDLC Registers
) time before
Data Sheet
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