XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 222
XC912BC32CFU8
Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
1.XC912BC32CFU8.pdf
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Serial Interface
14.4.2 Port S Data Direction Register
Data Sheet
222
Read: Anytime
Write: Anytime
After reset, all general-purpose I/O are configured for input only.
DDS0 — Data Direction for Port S Bit 0
DDS1 — Data Direction for Port S Bit 1
DDS2 and DDS3 — Data Direction for Port S Bit 2 and Bit 3
DDS6–DDS4 — Data Direction for Port S Bits 6–4
DDS7 — Data Direction for Port S Bit 7
If the SCI receiver is configured for 2-wire SCI operation, corresponding port S
pins are input regardless of the state of these bits.
If the SCI transmitter is configured for 2-wire SCI operation, corresponding port
S pins are output regardless of the state of these bits.
These bits are for general-purpose only.
If the SPI is enabled and expects the corresponding port S pin to be an input, it
will be an input regardless of the state of the DDRS bit. If the SPI is enabled and
expects the bit to be an output, it will be an output only if the DDRS bit is set.
In SPI slave mode, DDS7 has no meaning or effect; the PS7 pin is dedicated as
the SS input. In SPI master mode, DDS7 determines whether PS7 is an error
detect input to the SPI or a general-purpose or slave select output line.
Address:
Reset:
Read:
Write:
0 = Configure the corresponding I/O pin for input only.
1 = Configure the corresponding I/O pin for output.
Figure 14-21. Port S Data Direction Register (DDRS)
$00D7
DDS7
Bit 7
0
DDS6
6
0
Serial Interface
DDS5
5
0
DDS4
4
0
DDS3
3
0
M68HC12B Family — Rev. 8.0
DDS2
2
0
DDS1
1
0
MOTOROLA
DDS0
Bit 0
0
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