XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 144
XC912BC32CFU8
Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
1.XC912BC32CFU8.pdf
(362 pages)
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Pulse-Width Modulator (PWM)
11.2.12 PWM Control Register
Data Sheet
144
state. If the register is written while the channel is enabled, the new value is held
in a buffer until the counter rolls over or the channel is disabled. Reading this
register returns the most recent value written.
If the duty register is greater than or equal to the value in the period register, there
is no duty change in state. If the duty register is set to $FF, the output is always in
the state which would normally be the state opposite the PPOLx value.
Left-aligned output mode (CENTR = 0):
Center-aligned output mode (CENTR = 1):
Read: Anytime
Write: Anytime
PSWAI — PWM Halts While in Wait Mode Bit
CENTR — Center-Aligned Output Mode Bit
RDPP — Reduced Drive of Port P Bit
PUPP — Pullup Port P Enable Bit
PSBCK — PWM Stops While in Background Mode Bit
Duty cycle = [(PWDTYx + 1) / (PWPERx + 1)] × 100%
Duty cycle = [(PWPERx − PWDTYx) / (PWPERx + 1)] × 100%
Duty cycle = [(PWPERx − PWDTYx) / PWPERx] × 100%
Duty cycle = (PWDTYx / PWPERx) × 100%
To avoid irregularities in the PWM output mode, write the CENTR bit only when
PWM channels are disabled.
Address: $0054
Reset:
Read:
Write:
0 = Continue PWM main clock generator while in wait mode.
1 = Halt PWM main clock generator when the part is in wait mode.
0 = PWM channels operate in left-aligned output mode.
1 = PWM channels operate in center-aligned output mode.
0 = Full drive for all port P output pins
1 = Reduced drive for all port P output pins
0 = Disable port P pullups
1 = Enable pullups for all port P input pins.
0 = Allows PWM to continue while in background mode
1 = Disable PWM input clock while in background mode.
Bit 7
0
0
Figure 11-24. PWM Control Register (PWCTL)
Pulse-Width Modulator (PWM)
= Unimplemented
6
0
0
5
0
0
PSWAI
4
0
CENTR
3
0
M68HC12B Family — Rev. 8.0
RDPP
2
0
(PPOLx = 1)
(PPOLx = 0)
(PPOLx = 0)
(PPOLx = 1)
PUPP
1
0
MOTOROLA
PSBCK
Bit 0
0
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