XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 243

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

15.7.4.7 Invalid Active Bit
15.7.4.8 Valid Active Logic 1
15.7.4.9 Valid Active Logic 0
15.7.4.10 Valid SOF Symbol
15.7.4.11 Valid BREAK Symbol
M68HC12B Family — Rev. 8.0
MOTOROLA
In
data bit (or symbol) occurs between the passive-to-active transition beginning the
current data bit (or symbol) and A, the current bit would be invalid.
In
data bit (or symbol) occurs between A and B, the current bit would be considered
a logic 1.
In
data bit (or symbol) occurs between B and C, the current bit would be considered
a logic 0.
In
data bit (or symbol) occurs between C and D, the current symbol would be
considered a valid SOF symbol.
In
after E, the current symbol is considered a valid BREAK symbol. A BREAK symbol
should be followed by a start-of-frame (SOF) symbol beginning the next message
to be transmitted onto the J1850 bus. See
response to BREAK symbols.
Figure
Figure
Figure
Figure
Figure
ACTIVE
PASSIVE
15-9, if the next active-to-passive received transition does not occur until
15-8(1), if the active-to-passive received transition beginning the next
15-8(2), if the active-to-passive received transition beginning the next
15-8(3), if the active-to-passive received transition beginning the next
15-8(4), if the active-to-passive received transition beginning the next
Figure 15-9. J1850 VPW Received BREAK Symbol Times
Byte Data Link Communications (BDLC)
240 µs
15.7.2 J1850 Frame Format
Byte Data Link Communications (BDLC)
E
BDLC MUX Interface
(2) VALID BREAK SYMBOL
for BDLC
Data Sheet
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