LPC3130 Philips Semiconductors (Acquired by NXP), LPC3130 Datasheet - Page 34

• Manufacturer Part Number: LPC3130
• Manufacturer: Philips Semiconductors (Acquired by NXP)

NXP Semiconductors
LPC3130_3131_0
Preliminary data sheet
6.29 System control registers
6.30 I
The System Control Registers (SysCReg) module provides a register interface for some
of the high-level settings in the system such as multiplexers and mode settings. This is an
auxiliary module included in this overview for the sake of completeness.
The I
2
•
•
•
•
•
•
•
•
•
•
•
•
S0/1 interfaces
Audio interface compatible with the I
I
I
Supports LSB justified words of 16, 18, 20 and 24 bits.
Supports a configurable number of bit clock periods per Word Select period (up to 128
bit clock periods).
Supports DMA transfers.
Transmit FIFO (I
Supports single 16 bit transfers to/from the left or right FIFO.
Supports single 24 bit transfers to/from the left or right FIFO.
Supports 32-bit interleaved transfers, with the lower 16 bits representing the left audio
sample, and the higher 16 bits representing the right audio sample.
Supports two 16-bit audio samples combined in a 32-bit word (2 left or 2 right
samples) to reduce busload.
Provides maskable interrupts for audio status: FIFO underrun/overrun/full/
half_full/not empty for left and right channel separately.
2
2
2
S0/1 receive supports master mode and slave mode.
S0/1 transmit supports master mode.
S0/1 receive and I
Rev. 0.08 — 25 September 2008
2
S transmit) or receive FIFO (I
2
S0/1 transmit modules have the following features:
2
S standard.
2
S receive) of 4 stereo samples.
LPC3130/3131
© NXP B.V. 2008. All rights reserved.
34 of 60