LPC3130 Philips Semiconductors (Acquired by NXP), LPC3130 Datasheet - Page 19

• Manufacturer Part Number: LPC3130
• Manufacturer: Philips Semiconductors (Acquired by NXP)

NXP Semiconductors
LPC3130_3131_0
Preliminary data sheet
6.11 DMA controller
The DMA Controller can perform DMA transfers on the AHB bus without using the CPU.
This module has the following features:
Table 8:
Peripheral name
NAND flash controller
SPI
MCI
LCD interface
UART
I
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
C0/1 master/slave
Supports all high-speed USB-compliant peripherals.
Supports all full-speed USB-compliant peripherals.
Supports software Host Negotiation Protocol (HNP) and Session Request Protocol
(SRP) for OTG peripherals.
Contains UTMI+ compliant transceiver (PHY).
Supports Interrupts.
This module has its own, integrated DMA engine.
Supported transfer types:
Memory to memory:
– Memory can be copied from the source address to the destination address with a
Memory to peripheral:
– Data is transferred from incrementing memory to a fixed address of a peripheral.
Peripheral to memory:
– Data is transferred from a fixed address of a peripheral to incrementing memory.
Supports single data transfers for all transfer types.
Supports burst transfers for memory to memory transfers. A burst always consists of
multiples of 4 (32 bit) words.
The DMA controller has 12 channels.
Scatter-gather is used to gather data located at different areas of memory. Two
channels are needed per scatter-gather action.
Supports byte, half word and word transfers, and correctly aligns it over the AHB bus.
Compatible with ARM flow control for single requests (sreq), last single requests
(lsreq), terminal count info (tc), and dma clearing (clr).
Supports swapping in endianess of the transported data.
specified length, while incrementing the address for both the source and
destination.
The flow is controlled by the peripheral.
The flow is controlled by the peripheral.
Peripherals that support DMA access
Rev. 0.08 — 25 September 2008
Supported Transfer Types
Memory to memory
Memory to peripheral and peripheral to memory
Memory to peripheral and peripheral to memory
Memory to peripheral
Memory to peripheral and peripheral to memory
Memory to peripheral and peripheral to memory
LPC3130/3131
© NXP B.V. 2008. All rights reserved.
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