LPC3130 Philips Semiconductors (Acquired by NXP), LPC3130 Datasheet - Page 24

• Manufacturer Part Number: LPC3130
• Manufacturer: Philips Semiconductors (Acquired by NXP)

NXP Semiconductors
LPC3130_3131_0
Preliminary data sheet
Within most clock domains, the output clocks are again grouped into one or more
subdomains. All output clocks within one subdomain are either all generated by the same
fractional divider or they are connected directly to the base clock. Therefore all output
clocks within one subdomain have the same frequency and all output clocks within one
clock domain are synchronous because they originate from the same base clock
The CGU reference clock is generated by the external crystal. In addition, the CGU has
several Phase Locked Loop (PLL) circuits to generate clock signals that can be used for
system clocks and/or audio clocks. All clock sources, except the output of the PLLs, can
be used as reference input for the PLLs.
This module has the following features:
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Advanced features to optimize the system for low power:
– All output clocks can be disabled individually for flexible power optimization
– Some modules have automatic clock gating: they are only active when bus access
– Variable clock scaling for automatic power optimization of the AHB bus (high clock
– Clock wake-up feature: module clocks can be programmed to be activated
Supports five clock sources:
– Reference clock generated by the oscillator with an external crystal.
– Pins I2SRX_BCK0, I2SRX_WS0, I2SRX_BCK1 and I2SRX_WS1 are used to input
Two PLLs:
– System PLL generates programmable system clock frequency from its reference
– I
Highly flexible switchbox to distribute the signals from the clock sources to the module
clocks.
– Each clock generated by the CGU is derived from one of the base clocks and
– Each base clock can be programmed to have any one of the clock sources as an
– Fractional dividers can be used to divide a base clock by a fractional number to a
– Fractional dividers support clock stretching to obtain a (near) 50% duty cycle
Register interface to reset all modules under software control.
to the module is required.
frequency when the bus is active, low clock frequency when the bus is idle).
automatically on the basis of an event detected by the Event Router (see also
Section
activated automatically when a button is pressed.
external clock signals (used for generating audio frequencies in I2SRX slave
mode, see also
input.
reference input.
Remark: Both the System PLL and the I
on their (individual) reference clocks. The reference clocks can be programmed to
the oscillator clock or one of the external clock signals.
optionally divided by a fractional divider.
input clock.
lower clock frequency.
output clock.
2
S PLL generates programmable audio clock frequency (typically 256 × fs) from its
6.19). For example, all clocks (including the ARM /bus clocks) are off and
Rev. 0.08 — 25 September 2008
Section
6.4).
2
S PLL generate their frequencies based
LPC3130/3131
© NXP B.V. 2008. All rights reserved.
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