LPC3130 Philips Semiconductors (Acquired by NXP), LPC3130 Datasheet - Page 16

• Manufacturer Part Number: LPC3130
• Manufacturer: Philips Semiconductors (Acquired by NXP)

NXP Semiconductors
LPC3130_3131_0
Preliminary data sheet
6.5 Multi-Port Memory Controller (MPMC)
The multi-port memory controller supports the interface to different memory types, for
example:
This module has the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Software control mode where the ARM is directly master of the flash device.
Support for 8 bit and 16 bit flash devices.
Support for any page size from 0.5 kB upwards.
Programmable NAND flash timing parameters.
Support for up to 4 NAND devices.
Error Correction Module (ECC) for MLC NAND flash support:
– Reed-Solomon error correction encoding and decoding.
– Uses Reed-Solomon code words with 9-bit symbols over GF(2
– Up to 8 symbol errors can be corrected per codeword.
– Error correction can be turned on and off to match the demands of the application.
– Parity generator for error correction encoding.
– Wear leveling information can be integrated into protected data.
– Interrupts generated after completion of error correction task with 3 interrupt
– Error correction statistics distributed to ARM using interrupt scheme.
– Interface is compatible with the ARM External Bus Interface (EBI).
SDRAM
Low-power SDRAM
Static memory interface
Dynamic memory interface support including SDRAM, JEDEC low-power SDRAM.
Address line supporting up to 64 MB of dynamic memory.
The MPMC has two AHB interfaces:
a. an interface for accessing external memory.
b. a separate control interface to program the MPMC. This enables the MPMC
Low transaction latency.
Read and write buffers to reduce latency and to improve performance, particularly for
un-cached processors.
Static memory features include:
– asynchronous page mode read
– programmable wait states
– bus turnaround delay
– output enable and write enable delays
length of 469 symbols, including 10 parity symbols, giving a minimum Hamming
distance of 11.
registers.
registers to be situated in memory with other system peripheral registers.
Rev. 0.08 — 25 September 2008
LPC3130/3131
9
), a total codeword
© NXP B.V. 2008. All rights reserved.
16 of 60