LPC3130 Philips Semiconductors (Acquired by NXP), LPC3130 Datasheet - Page 11

• Manufacturer Part Number: LPC3130
• Manufacturer: Philips Semiconductors (Acquired by NXP)

NXP Semiconductors
Table 4.
Pin names with prefix m are multiplexed pins. See
[1]
[2]
[3]
[4]
LPC3130_3131_0
Preliminary data sheet
Pin name
External Bus Interface (NAND flash controller)
EBI_A_0_ALE
EBI_A_1_CLE
EBI_D_0
EBI_D_1
EBI_D_2
EBI_D_3
EBI_D_4
EBI_D_5
EBI_D_6
EBI_D_7
EBI_D_8
EBI_D_9
EBI_D_10
EBI_D_11
EBI_D_12
EBI_D_13
EBI_D_14
EBI_D_15
EBI_DQM_0_NOE
EBI_NWE
NAND_NCS_0
NAND_NCS_1
NAND_NCS_2
NAND_NCS_3
mNAND_RYBN0
mNAND_RYBN1
mNAND_RYBN2
mNAND_RYBN3
EBI_NCAS_BLOUT_0
EBI_NRAS_BLOUT_1
Pulse Width Modulation module
PWM_DATA
Digital IO levels are explained in
Cell types are explained in
Pin can be configured as GPIO pin in the IOCONFIG block.
The UART flow control lines (mUART_CTS_N and mUART_RTS_N) are multiplexed. This means that if these balls are not required for
UART flow control, they can also be selected to be used for an alternative function: SPI chip select signals (SPI_CS_OUT1 and
SPI_CS_OUT2)
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
Pin description
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
BGA
Ball
B3
A2
G2
F2
F1
E1
E2
D1
D2
C1
B1
A3
A1
C2
G3
D3
E3
F3
H1
J2
J1
J3
K1
K2
E6
E7
B4
D4
G1
H2
B9
Table
Table
6.
Digital
I/O
level
[1]
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP3
5.
Application
function
DO
DO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DO
DO
DO
DO
DO
DO
DI
DI
DI
DI
DO
DO
DO / GPIO
Rev. 0.08 — 25 September 2008
Table 9
Pin
state
after
reset
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
I
I
I
I
O
O
O
for pin function selection of multiplexed pins.
Cell
Type
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO1
[2]
Description
EBI Address Latch Enable
EBI Command Latch Enable
EBI Data I/O 5
EBI Data I/O 6
EBI Data I/O 7
EBI Data I/O 11
EBI Data I/O 12
EBI Data I/O 13
NAND Read Enable (active low)
NAND Write Enable (active low)
NAND Chip Enable 0
NAND Chip Enable 1
NAND Chip Enable 2
NAND Chip Enable 3
NAND Ready/Busy 0
NAND Ready/Busy 1
NAND Ready/Busy 2
NAND Ready/Busy 3
EBI Lower lane byte select (7:0)
EBI Upper lane byte select (15:8)
PWM Output
EBI Data I/O 0
EBI Data I/O 1
EBI Data I/O 2
EBI Data I/O 3
EBI Data I/O 4
EBI Data I/O 8
EBI Data I/O 9
EBI Data I/O 10
EBI Data I/O 14
EBI Data I/O 15
LPC3130/3131
© NXP B.V. 2008. All rights reserved.
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