LPC3130 Philips Semiconductors (Acquired by NXP), LPC3130 Datasheet - Page 20

• Manufacturer Part Number: LPC3130
• Manufacturer: Philips Semiconductors (Acquired by NXP)

NXP Semiconductors
LPC3130_3131_0
Preliminary data sheet
6.12 Interrupt controller
Table 8:
The Interrupt Controller (INTC) collects interrupt requests from multiple devices, masks
interrupt requests, and forwards the combined requests to the processor (see
The interrupt controller also provides facilities to identify the interrupt requesting devices
to be served.
This module has the following features:
The following blocks can generate interrupts:
Peripheral name
I
I
PCM interface
2
2
Fig 5. Block diagram of the interrupt controller
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S0/1 receive
S0/1 transmit
The interrupt controller decodes all the interrupt requests issued by the on-chip
peripherals.
Two interrupt lines (nFIQ, nIRQ) to the ARM core. The ARM core supports two distinct
levels of priority on all interrupt sources, nFIQ for high priority interrupts and nIRQ for
normal priority interrupts.
Software interrupt request capability associated with each request input.
Visibility of the interrupt’s request state before masking.
Support for nesting of interrupt service routines.
Interrupts routed to nIRQ and to nFIQ are vectored.
Level interrupt support.
NAND flash controller
USB 2.0 HS OTG
Event router
10-bit ADC
UART
LCD
MCI
SPI
Timer0, Timer1, Timer2, and Timer3
I
2
C0 and I
Peripherals that support DMA access
requests
interrupt
2
C1
Rev. 0.08 — 25 September 2008
INTERRUPT CONTROLLER
Supported Transfer Types
Peripheral to Memory
Memory to peripheral
Memory to peripheral and peripheral to memory
nIRQ
nFIQ
LPC3130/3131
ARM926EJ-S
002aae084
© NXP B.V. 2008. All rights reserved.
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