AD9510 Analog Devices, AD9510 Datasheet - Page 5

• Manufacturer Part Number: AD9510
• Manufacturer: Analog Devices

Preliminary Technical Data
CLOCK OUTPUTS
Table 3.
Parameter
LVPECL CLOCK OUTPUTS
LVDS CLOCK OUTPUTS
CMOS CLOCK OUTPUTS
TIMING CHARACTERISTICS
Table 4.
Parameter
LVPECL
CLK-TO-LVPECL OUT
OUT0, OUT1 OUT2, OUT3; Differential
Output Frequency
Output High Voltage (V
Output Low Voltage (V
Output Differential Voltage (V
Isolation LVPECL to LVPECL Output
Isolation LVDS to LVPECL Output
Isolation CMOS to LVPECL Output
OUT4, OUT5, OUT6, OUT7; Differential
Output Frequency
Differential Output Voltage (V
Delta V
Output Offset Voltage (V
Delta V
Short-Circuit Current (I
Isolation LVDS to LVDS
Isolation LVPECL to LVDS
Isolation CMOS to LVDS
OUT4, OUT5, OUT6, OUT7; Single Ended
Output Frequency
Output Voltage High (V
Output Voltage Low (V
Isolation CMOS to CMOS
Isolation LVPECL to CMOS
Isolation LVDS to CMOS
Output Rise Time, t
Output Fall Time, t
Propagation Delay, t
Output Skew, t
Output Skew, t
Divide = Bypass
Divide = 2 − 32
OD
OS
SKP
SKP_AB
FP
RP
PECL
SA
OL
OL
OH
OH
, I
)
)
OS
)
)
SB
)
)
OD
OD
)
)
Min
V
V
S
S
Min
− 1.2
− 1.8
Rev. PrA | Page 5 of 41
Typ
120
120
0.65
0.65
25
150
Typ
800
350
5
1.25
5
13
2.7
0.4
Max
50
300
Max
800
V
V
800
250
S
S
− 0.8
− 1.6
Unit
ps
ps
ns
ns
ps
ps
Unit
MHz
V
V
mV
dB
dB
dB
MHz
mV
mV
V
mV
mA
dB
dB
dB
MHz
V
V
dB
dB
dB
Test Conditions/Comments
Termination = 50 Ω to V
Output level setting 3C (3D) (3E) (3F) <3:2> = 10
20% to 80%
80% to 20%
CLK1 or CLK2
LVPECL to LVPECL on same part
LVPECL to LVPECL on different parts
Test Conditions/Comments
Termination = 50 Ω to V
Output level setting 3C (3D) (3E) (3F)
<3:2> = 10
@ dc
@ dc
@ dc
100 MHz output with 50 MHz aggressor
100 MHz output with 50 MHz aggressor
100 MHz output with 50 MHz aggressor
Termination = 100 Ω differential; default
Output Level setting 40 (41) (42) (43)
<2:1> = 01, 3.5 mA termination current
Output shorted to GND
100 MHz output with 50 MHz aggressor
100 MHz output with 50 MHz aggressor
100 MHz output with 50 MHz aggressor
B outputs are inverted;
termination = open
5 pF load
100 MHz output with 50 MHz aggressor
100 MHz output with 50 MHz aggressor
100 MHz output with 50 MHz aggressor
S
− 2 V; default
S
− 2 V; default
1
2
AD9510