AD9510 Analog Devices, AD9510 Datasheet - Page 33

• Manufacturer Part Number: AD9510
• Manufacturer: Analog Devices

Reg.
Addr.
(Hex)
0D
0D
0E-33
34
(38)
34
(38)
35
(39)
35
(39)
36
(3A)
37
(3B)
Preliminary Technical Data
Bit(s)
<6>
<7>
<0>
<7:1>
<2:0>
<5:3>
<5:0>
<2:0>
Lock Detect Disable
Unused
Fine Delay Adjust
OUT5
(OUT6)
Ramp Control
OUT5
(OUT6)
Ramp Control
OUT5
(OUT6)
OUT5
(OUT6)
OUT5
(OUT6)
Name
Delay Control
Reference Value
Delay Fine Tune
Description
If the time difference of the rising edges at the inputs to the PFD are less than the lock detect
window time, the digital lock detect flag is set. The flag remains set until the time difference is
greater than loss-of-lock threshold.
0 = normal lock detect operation (default).
1 = disable lock detect.
Reserved or not used.
Reserved or not used.
Delay block control bit.
Bypasses delay block and powers it down (default = 1).
Reserved or not used.
The slowest ramp (200 µs) sets the longest full scale of approximately 10 ns.
<2>
0
0
0
0
1
1
1
1
Selects the number of capacitors in ramp generation circuit.
More capacitors => slower ramp.
<5>
0
0
0
0
1
1
1
1
Sets delay within full scale of the ramp. There are 64 steps to control the reference value for the
comparator.
000000 => zero delay (default).
111111 => maximum delay.
The delay fine tune slightly increases or decreases the ramp current (−8% to +13%) to negate
the process variation of the caps. Defaults to 100, which is the midpoint.
Rev. PrA | Page 33 of 41
<1>
0
0
1
1
0
0
1
1
<4>
0
0
1
1
0
0
1
1
<0>
0
1
0
1
0
1
0
1
<3>
0
1
0
1
0
1
0
1
Number of Capacitors
4 (Default)
3
3
2
3
2
2
1
Ramp Current (µs)
200
400
600
800
1000
1200
1400
1600
AD9510