AD9510 Analog Devices, AD9510 Datasheet - Page 30

• Manufacturer Part Number: AD9510
• Manufacturer: Analog Devices

Reg.
Addr.
(Hex)
00
00
00
00
00
00
00
00
01
02
03
04
04
05
05
06
07
07
07
07
07
AD9510
REGISTER MAP DESCRIPTION
The is a detailed description of each of the control register functions. The registers are listed by hexadecimal address. Reference to a
specific bit or range of bits within a register is accomplished by the use of angle brackets. For example, <3> refers to Bit 3, while <5:2>
refers to the range of bits from Bit 5 through Bit 2. Table 20 describes the functionality of the control registers on a bit-by-bit basis. For a
more concise (but less descriptive) table see Table 19.
Table 20. AD9510 Register Descriptions
Bit(s)
<0>
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<7:0>
<7:0>
<7:0>
<5:0>
<7:6>
<4:0>
<7:5>
<7:0>
<1:0>
<2>
<4:3>
<6:5>
<7>
Name
Serial Control Port
Configuration
SDO Active
LSB First
Soft Reset
Long Instruction
Long Instruction
Soft Reset
LSB First
SDO Active
Unused
PLL Settings
A Counter
B Counter MSBs
B Counter LSBs
LOR Enable
LOR Initial Lock Detect
Delay
Description
Note: <7:4> mirror <3:0> to ensure that this register can be accessed regardless of the state of
<1> or <6> (the bit that sets LSB first).
When set causes SDO to become active. When clear, the SDO pin remains in tri-state and all
read data is routed to the SDIO pin. (Default = 0.)
When set causes input and output data to be oriented as LSB first. Additionally, addressing
increments. If this bit is clear, data is oriented as MSB first and addressing decrements. (Default
= 0, MSB first.)
When a 1 is written to this bit, the chip executes a soft reset, restoring default values to all of
the internal registers.
This bit is self-clearing. A 0 does not have to be written to clear it.
When set, the instruction phase is 16 bits. When clear, the instruction phase is 8 bits.
The default, and only, mode for this part is long instruction. (Default = 1.)
Same as <3>.
Same as <2>.
Same as <1>.
Same as <0>.
Reserved or not used.
Reserved or not used.
Reserved or not used.
6-bit A counter <5:0>.
Reserved or not used.
13-bit B counter (MSB) <12:8>.
Reserved or not used.
13-bit B counter (LSB) <7:0>.
Reserved or not used.
1 = enables the loss of reference (LOR) function; (Default = 0).
Reserved or not used (default = 00).
LOR initial lock detect delay. Once a lock detect is indicated, this is the number of phase
frequency detector (PFD) cycles that occur prior to turning on the LOR monitor.
<6>
0
0
1
1
Reserved or not used
Rev. PrA | Page 30 of 41
<5>
0
1
0
1
Preliminary Technical Data
LOR Initial Lock Deteck Delay
3 PFD Cycles (Default)
6 PFD Cycles
12 PFD Cycles
24 PFD Cycles