AD9510 Analog Devices, AD9510 Datasheet - Page 35

• Manufacturer Part Number: AD9510
• Manufacturer: Analog Devices

Reg.
Addr.
(Hex)
40
(41)
(42)
(43)
40
(41)
(42)
(43)
40
(41)
(42)
(43)
44
45
45
45
45
45
45
45
46
47
48
(4A)
(4C)
(4E)
(50)
(52)
(54)
(56)
Preliminary Technical Data
Bit(s)
<3>
<4>
<7:5>
<7:0>
<0>
<1>
<2>
<3>
<4>
<5>
<7:6>
<7:0>
<7:0>
<3:0>
OUT4
(OUT5)
(OUT6)
(OUT7)
OUT4
(OUT5)
(OUT6)
(OUT7)
Prescaler Clock Power-
Down
All Clock Inputs Power-
Down
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
(OUT5)
(OUT6)
(OUT7)
Name
LVDS/CMOS Select
Inverted CMOS Driver
Clock Select
CLK1 Power-Down
CLK2 Power-Down
REFIN Power-Down
Divider High
Description
<2>
0
0
1
1
0 = LVDS (default).
1 = CMOS.
Affects output only when in CMOS mode.
0 = disable inverted CMOS driver (default).
1 = enable inverted CMOS driver.
Reserved or not used.
Reserved or not used.
0: CLK2 drives distribution section.
1: CLK1 drives distribution section (default).
1 = CLK1 input is powered down (default = 0).
1 = CLK2 input is powered down (default = 0).
1 = shut down clock signal to PLL prescaler (default = 0).
1 = power-down REFIN (default = 0).
1 = power-down CLK1 and CLK2 inputs and associated bias and internal clock tree;
(default = 0).
Reserved or not used.
Reserved or not used.
Reserved or not used.
Number of clock cycles divider output stays high.
Rev. PrA | Page 35 of 41
<1>
0
1
0
1
Current (mA)
1.75
3.5 (Default)
5.25
7
Termination (Ω)
100
100
50
50
AD9510