AD9510 Analog Devices, AD9510 Datasheet - Page 11

• Manufacturer Part Number: AD9510
• Manufacturer: Analog Devices

Preliminary Technical Data
SERIAL CONTROL PORT
Table 8.
Parameter
SDIO, CSB, SCLK
SDIO, SDO
CSB, SCLK
TIMING
FUNCTION PIN
Table 9.
Parameter
INPUT CHARACTERISTICS
RESET TIMING
SYNC TIMING
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Capacitance
Output Logic 1 Voltage
Output Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Clock Rate (SCLK, 1/t
Pulse-Width High, t
Pulse-Width Low, t
SDIO and CSB to SCLK Setup, t
SCLK to SDIO Hold, t
SCLK to Valid SDIO and SDO, t
Logic 1 Voltage
Logic 0 Voltage
Input Capacitance
Logic 1 Current
Logic 0 Current
Pulse-Width Low
Pulse-Width Low
Setup Time
Hold Time
PWL
PWH
DH
SCLK
)
DV
DS
Min
1.5
Min
16
16
CMOS Levels
Typ
Typ
CMOS Levels
CMOS Levels
CMOS Levels
Rev. PrA | Page 11 of 41
Max
25
24
24
Max
Unit
V
V
pF
µA
µA
ns
Clock cycles
ps
ps
Unit
V
V
pF
V
V
µA
µA
MHz
ns
ns
ns
ns
ns
Test Conditions/Comments
CSB and SCLK have 30 kΩ internal pull-down resistors
Test Conditions/Comments
Sync single chip; CLK1 or CL2,
whichever is being used for distribution
Sync multichip; Write CLK1 or CLK2,
whichever is being used for distribution
Sync multichip; Write CLK1 or CLK2,
whichever is being used for distribution
AD9510