AD9510 Analog Devices, AD9510 Datasheet - Page 12

• Manufacturer Part Number: AD9510
• Manufacturer: Analog Devices

AD9510
STATUS PIN
Table 10.
Parameter
OUTPUT CHARACTERISTICS
MAXIMUM TOGGLE RATE
ANALOG LOCK DETECT
POWER
Table 11.
Parameter
POWER-UP DEFAULT MODE POWER DISSIPATION
MAXIMUM POWER DISSIPATION
POWER DELTA
Output Voltage High (V
Output Voltage Low (V
Capacitance
CLK1, CLK2 Power-Down
Divider, DIV 2 − 32 to Bypass
LVPECL Output Power-Down
LVDS Output Power-Down
CMOS Output Power-Down
Delay Block Bypass
Delay Block Power-Down
PLL Section Power-Down
Safe Power-Down (PD2)
Total Power-Down (PD3)
OL
OH
)
)
Min
Typ
3
Max
100
Min
Unit
mV
mV
MHz
pF
Rev. PrA | Page 12 of 41
Typ
650
1050
56
58
33
24
40
Test Conditions/Comments
Applies when PLL mux is set to any divider or counter output,
or PFD up/down pulse. Also applies in analog lock detect mode.
Usually debug mode only. Beware that spurs may couple
to output when this pin is toggling.
On-chip capacitance; used to calculate RC time
constant for analog lock detect readback. Use pull-up resistor.
Max
46
38
Unit
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
Power-up default state; does not
include power dissipated in output
load resistors.
All functions enabled, all outputs on
and terminated, maximum clock rates,
and frequencies. Does not include
power dissipated in load resistors.
(Pick these conditions.)
PD2 mode (safe) power-down is required
when load resistors are connected. Delta
does not include dissipation in load resistors.
PD3 mode; use only with no load resistors connected.
Test Conditions/Comments
Preliminary Technical Data