AD9510 Analog Devices, AD9510 Datasheet - Page 23

• Manufacturer Part Number: AD9510
• Manufacturer: Analog Devices

Preliminary Technical Data
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter
(N = BP + A) and produces an output proportional to the phase
and frequency difference between them. Figure 14 is a
simplified schematic. The PFD includes a programmable delay
element that controls the width of the antibacklash pulse. This
pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. Two
bits in Register 0D <1:0> control the width of the pulse.
STATUS PIN
The output multiplexer on the AD9510 allows access to various
internal points on the chip. The state of the STATUS pin is
controlled by Register 08 <5:2>. Figure 15 shows the STATUS
pin section in block diagram form.
Lock Detect
The STATUS pin can be programmed for two types of lock
detect: digital and analog.
See Table 20 OD <5> for the description of this function.
The N-channel, open-drain, analog lock detect should be
operated with an external pull-up resistor of 30 kΩ nominal.
When lock is detected, the output is high with narrow, low
going pulses.
R DIVIDER
N DIVIDER
Figure 14. PFD Simplified Schematic and Timing (In Lock)
HI
HI
D2
D1
CLR1
CLR2
U2
U1
Q1
Q2
PROGRAMMABLE
UP
DOWN
Antibacklash
pulse width
DELAY
U3
GND
V
P
CHARGE
PUMP
Rev. PrA | Page 23 of 41
CP
Loss o reference or Lock Detec (active high)
CLK1 CLOCK INPUT
CLK1 is the distribution only clock input. This clock input is
selected by default on power-up. It is usable for inputs up to
1500 MHz.
CLK2 is electrically identical but feeds the PLL N divider as well
as being selectable as the input for the distribution section
through the clock select MUX.
If the distribution section is being used only, it is recommended
that the unselected clock input be powered down in order to
eliminate any possibility of unwanted crosstalk between the
selected clock input and the unselected clock input.
CLKB
Loss o reference or Lock Detec (active low)
CLK
VS
Analog Lock Detec (p-channel open drain)
Analog Lock Detec (n-channel open drain)
Digital Lock Detec (active high)
Digital Lock Detec (active low)
Loss o Reference (active high)
Loss o Reference (active low)
5k
5k
2.5k
Prescaler Outpu (NCLK)
Figure 16. CLK1, CLK2 Equivalent Input Circuit
A Counter Output
PFD Down Pulse
Off (low) (default)
N Divider Output
PFD U Pulse
PLL MUX CONTROL
08h <5:2>
TriState
Figure 15. STATUS Pin Circuit
2.5k
Sync Detect
SYNC DETECT ENABLE
Clock input
stage
58h <0>
AD9510
GND
V
S
STATUS
pin