AD9510 Analog Devices, AD9510 Datasheet - Page 21

• Manufacturer Part Number: AD9510
• Manufacturer: Analog Devices

Preliminary Technical Data
FUNCTION DESCRIPTION
OVERALL
Figure 13 shows a block diagram of the AD9510. The chip
combines a programmable PLL core with a configurable clock
distribution system. A complete PLL requires the addition of a
suitable external VCO (or VCXO) and loop filter. This PLL can
be used to lock to a reference input signal and produce an
output that is related to the input frequency by the ratio defined
by the programmable R and N dividers. The PLL offers some
jitter clean up of the external reference signal, depending on the
loop bandwidth and the phase noise performance of the VCO
(VCXO).
The output from the VCO (VCXO) can be applied to the clock
distribution section of the chip, where it can be divided by any
integer value from 1 to 32. The duty cycle and relative phase of
the outputs can be selected. There are four LVPECL outputs,
(OUT0, OUT1, OUT2, and OUT3) and four outputs that can be
selected as either LVDS or CMOS level outputs (OUT4, OUT5,
OUT6, and OUT7). Two of these outputs (OUT5, OUT6) can
also make use of a variable delay block.
Alternatively, the clock distribution section can be driven
directly by an external clock signal, and the PLL can be powered
off. Whenever the clock distribution section is used alone, there
is no clock clean-up. The jitter of the input clock signal is passed
along directly to the distribution section and may dominate at
the clock outputs.
PLL OPERATION
The AD9510 has a complete PLL core on-chip, requiring only
an external loop filter and VCO/VCXO. This PLL is based on
the ADF4106, a PLL noted for its superb low phase noise
performance. The operation of the AD9510 PLL is nearly
identical to that of the ADF4106, offering an advantage to those
with experience with the ADF series of PLLs. Differences
include the addition of differential inputs at REFIN and CLK2, a
different control register architecture, and the prescaler has
been changed to allow N as low as 1. The AD9510 PLL also
implements the digital lock detect feature somewhat differently
than does the ADF4106 offering improved functionality at
higher PFD rates. Refer to Register Map Description for details.
The PLL section can be used entirely separately from the
distribution system, if so desired.
PLL REFERENCE INPUT
The REFIN and REFINB pins can be driven differentially or
single-ended. These pins are internally self-biased, so they
should always be capacitively coupled. This also applies to the
unused side when single-ended input is used.
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PLL REFERENCE DIVIDER
The REFIN/REFINB inputs are routed to reference divider, R,
which is a 14-bit counter. R may be programmed to any value
from 0 to 16383 via its control register. The output of the R
divider goes to one of the phase/frequency detector inputs. The
maximum allowable frequency into the phase/frequency
detector (PFD) must not be exceeded. This means that the
REFIN frequency divided by R must be less than the maximum
allowable PFD frequency.
VCO/VCXO CLOCK INPUT
The CLK2 differential input may be used as a second
distribution input, or it may be used to connect an external
VCO or VCXO to the PLL . Only the CLK2 input port has a
connection to the PLL N divider. This input can receive up to
1.5 GHz. These inputs are internally self-biased and must be
capacitively coupled.
CLK1 is electrically identical, but normally feeds the
distribution section instead. See Figure 16 for the equivalent
circuit of CLK1/CLK2.
VCO/VCXO FEEDBACK DIVIDER
The N divider is a combination of a prescaler and two counters,
A and B. Although the AD9510’s PLL is similar to the ADF4106,
the AD9510 has a redesigned prescaler that allows for lower
values of N. The prescaler has both a dual modulus (DM) mode
and a fixed divide (FD) mode. The AD9510 prescaler modes are
shown in Table 14.
Table 14. PLL Prescaler Modes
Mode
(FD = Fixed Divide; DM = Dual Modulus)
FD
FD
P = 2 DM
P = 4 DM
P = 8 DM
P = 16 DM
P = 32 DM
FD
When using the prescaler in a FD mode, the A counter is not
used, and the B counter may need to be bypassed. The DM
prescaler modes set some upper limits on the frequency, which
can be applied to CLK2 . These are shown in Table 15.
Divide By
1
2
P/P + 1 = 2/3
P/P + 1 = 4/5
P/P + 1 = 8/9
P/P + 1 = 16/17
P/P + 1 = 32/33
3
AD9510