AD9510 Analog Devices, AD9510 Datasheet - Page 24

• Manufacturer Part Number: AD9510
• Manufacturer: Analog Devices

AD9510
SERIAL CONTROL PORT
The AD9510 serial control port is a flexible, synchronous, serial
communications port that allows an easy interface with many
industry-standard microcontrollers and microprocessors. The
AD9510 serial control port is compatible with most
synchronous transfer formats, including both the Motorola SPI®
and Intel® SSR protocols. The serial control port allows
read/write access to all registers that configure the AD9510.
Single or multiple byte transfers are supported, as well as MSB
first or LSB first transfer formats. The AD9510 serial control
port can be configured for single pin I/O (SDIO only) or two
unidirectional pins for in/out (SDIO/SDO).
SERIAL CONTROL PORT PIN DESCRIPTIONS
SCLK (serial clock) is the serial shift clock. This pin is an input.
SCLK is used to synchronize serial control port reads and
writes. Write data bits are registered on the rising edge of this
clock, and read data bits are registered on the falling edge. This
pin is internally pulled down by a 30 kΩ resistor to ground.
SDIO (serial data input/output) is a dual-purpose pin and acts
as either an input only in 4-wire mode or as an input/output in
3-wire mode. The AD9510 defaults to 3-wire mode (single pin
I/O—SDIO only). Four-wire mode (two unidirectional pins for
I/O – SDIO/SDO) may be enabled by setting 1 into the SDO
enable register at Address 00h, Bit <7>.
SDO (serial data out) is used in the 4-wire mode only as a
separate output pin for readback data. The AD9510 defaults to
3-wire mode. Four-wire mode may be enabled by setting 1 into
the SDO enable register at Address 00h, Bit <7>.
CSB (chip select bar) is an active low control that gates the read
and write cycles. When CSB is high, SDO and SDIO are in a
high impedance state. This pin is internally pulled down by a
30 kΩ resistor to ground.
GENERAL OPERATION OF SERIAL CONTROL PORT
There are three phases to a communication cycle with the
AD9510. Phase 1 is the instruction cycle, which is the writing of
a 16-bit instruction word into the AD9510, coincident with the
first 16 SCLK rising edges. The instruction word provides the
AD9510 serial control port with information regarding the data
transfer cycle (Phase 2) of the communication cycle. The
Phase 1 instruction word defines whether the upcoming data
transfer is read or write, the number of bytes in the data
transfer, and the starting register address for the first byte of the
data transfer.
SCLK (pin 18)
SDI0 (pin 19)
CSB (pin 21)
SD0 (pin 20)
Figure 17. Serial Control Port
CONTROL
AD9510
SERIAL
PORT
Rev. PrA | Page 24 of 41
Write
If the instruction word (Phase 1) is for a write operation
(I15 = 0), then Phase 2 is the transfer of data into the serial
control port buffer of the AD9510. The length of the transfer (1,
2, 3, or 4 data bytes) is indicated by 2 bits (W1:W0) in the
instruction byte. Multibyte data transfer is the preferred
method. Single byte data transfers are useful to reduce CPU
overhead when only one byte of data needs to be loaded. CSB
can be raised after each sequence of 8 bits (except the last byte)
to stall the bus. The serial transfer resumes when CSB is
lowered. Stalling on nonbyte boundaries resets the serial control
port.
Since data is written into a serial control port buffer area, not
directly into the AD9510’s actual control registers, a Phase 3
operation is needed in order to transfer the serial control port
buffer contents to the actual control registers of the AD9510,
thereby causing them to take effect. Phase 3 consists of writing a
high bit (one) to Address 5Ah, Bit <0>. This update bit is self-
clearing (it is not required to write a 0 to it in order to clear it).
Since any number of bytes of data may be changed before
issuing an update, the update simultaneously enables all register
changes since any previous update.
Read
If the instruction word (Phase 1) is for a read operation
(I15 = 1), the next N × 8 SCLK cycles clock out the data from
the address specified in the instruction word, where N is 1 to 4
as determined by W1:W0. The readback data is valid on the
falling edge of SCLK.
The default mode of the AD9510 serial control port is 3-wire
mode; therefore, the requested data normally appears on the
SDIO pin. It is possible to set the AD9510 to 4-wire mode by
setting 1 into the SDO enable register at Address 00h, Bit <7>.
In 4-wire mode, the readback data appears on the SDO pin.
A readback request reads the data that is in the serial control
port buffer area not the active data in the AD9510’s actual
control registers.
Figure 18. Relationship between Serial Control Port Register Buffers and
SCLK
SDIO
SDO
CSB
SERIAL
CONTROL
PORT
Control Registers of the AD9510
Preliminary Technical Data
* UPDATE
REGISTERS
5Ah <0>
AD9510 CORE