AD9510 Analog Devices, AD9510 Datasheet - Page 38

• Manufacturer Part Number: AD9510
• Manufacturer: Analog Devices

AD9510
APPLICATIONS
USING THE AD9510 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed analog-to-digital converter (ADC) is extremely
sensitive to the quality of the sampling clock provided by the
user. An ADC can be thought of as a sampling mixer; and any
noise, distortion, or timing jitter on the clock is combined with
the desired signal at the A/D output. Clock integrity
requirements scale with the analog input frequency and
resolution, with higher analog input frequency applications at
>= 14-bit resolution being the most stringent. The theoretical
SNR of an ADC is limited by the ADC resolution and the jitter
on the sampling clock. Considering an ideal ADC of infinite
resolution where the step size and quantization error can be
ignored, the available SNR is can be expressed approximately by
where f is the highest analog frequency being digitized, and t
the rms jitter on the sampling clock. The figure below shows
required sampling clock jitter as function of analog frequency
and effective number of bits (ENOB)
(See Application Note AN-501 at www.analog.com for more
information).
Many high performance ADC’s feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.) The
AD9510 features both LVPECL and LVDS outputs that provide
differential clock outputs, which enable clock solutions that
maximize converter SNR performance. The input requirements
of the ADC (differential or single-ended, logic level,
termination) should be considered when selecting the best
clocking/converter solution.
SNR
=
Figure 24. ENOB and SNR vs. Analog Input Frequency
20
×
log
⎡
⎢
⎣
2π
1
ft
J
⎤
⎥
⎦
Rev. PrA | Page 38 of 41
j
is
CMOS CLOCK DISTRIBUTION
The AD9510 provides four clock outputs (OUT4 to OUT7)
which are selectable as either CMOS or LVDS levels. When
selected as CMOS, these outputs provide a way to drive devices
requiring CMOS level logic at their clock inputs. Due to factors
inherent to CMOS logic, the jitter performance of these outputs
cannot equal that of the LVPECL and LVDS outputs. However,
for many clocking needs within a system, CMOS clock levels are
appropriate.
Whenever single-ended CMOS clocking is used, some of the
following general guidelines should be followed.
Point-to-point nets should be designed such that a driver only
has one receiver on the net, if possible. This allows for simple
termination schemes and minimize ringing due to possible
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line
matching and/or to reduce current transients at the driver. The
value of the resistor is dependent on board design and timing
requirements (typically 10 Ω to 100 Ω is used). CMOS outputs
are also limited in terms of the capacitive load or trace length
that they can drive, typically trace lengths less than 3 inches are
recommended to preserve signal rise/fall times and preserve
signal integrity. Simulation results for the AD9510 CMOS
outputs with a 1-inch and 3-inch trace load are shown in
Figure 26. In this example, the series resistor is 10 Ω and the
trace impedance is 60 Ω. Signal integrity, in this example, has
started to degrade already at a 3-inch trace length.
Figure 25. Series Termination of CMOS Output
Preliminary Technical Data