AD9510 Analog Devices, AD9510 Datasheet - Page 19

• Manufacturer Part Number: AD9510
• Manufacturer: Analog Devices

Preliminary Technical Data
TYPICAL MODES OF OPERATION
PLL with External VCXO/VCO Followed by Clock
Distribution
This is the most common operational mode for the AD9510. An
external oscillator (shown as VCO/VCXO) is phase locked to a
reference input frequency applied to REFIN. The loop filter is
usually a passive design. A VCO or a VCXO may be used. The
CLK2 input is connected internally to the feedback divider, N.
The CLK2 input provides the feedback path for the PLL. If the
VCO/VCXO frequency exceeds maximum frequency of the
output(s) being used, an appropriate divide ratio must be set in
the corresponding divider(s) in the distribution section.
Clock Distribution Only
In this mode, the PLL is not used. A customer can save power by
initiating a PLL power-down and by powering down any
unused clock channels.
In distribution mode, both CLK1 and CLK2 inputs are available
for distribution to outputs via a low jitter multiplexer (MUX).
Reference
Input
CLK1
REFIN
Figure 10. PLL and Clock Distribution Mode
Serial
Port
Function
Divide
Divide
Divide
Divide
Divide
Divide
Divide
Divide
Vref
R
N
AD9510
Status
PFD
∆T
∆T
PLL
Ref
LVPECL
LVPECL
LVPECL
LVPECL
CMOS
CMOS
CMOS
LVDS/
CMOS
LVDS/
LVDS/
LVDS/
CP
CLK2
Outputs
Clock
VCXO,
Loop
Filter
VCO
Rev. PrA | Page 19 of 41
PLL with External VCO and Band-Pass Filter Followed by
Clock Distribution
An external band-pass filter may be used to possibly improve
the phase noise and spurious characteristics of the PLL output.
This option is most appropriate when the desire is to optimize
cost by choosing a less expensive VCO combined with a
moderately priced filter. Note that the BPF is shown outside of
the VCO to N divider path, with the BP filter outputs routed to
CLK1.
Input 1
Clock
Reference
Input
REFIN
Serial
Port
CLK1
CLK1
REFIN
Figure 12. AD9510 with VCO and BPF Filter
Function
Serial
Port
Function
Figure 11. Clock Distribution Mode
Divide
Divide
Divide
Divide
Divide
Divide
Divide
Divide
Vref
Divide
Divide
Divide
Divide
Divide
Divide
Divide
Divide
Vref
R
N
R
N
AD9510
AD9510
Status
PFD
Status
PFD
∆T
∆T
∆T
∆T
PLL
Ref
LVPECL
LVPECL
LVPECL
CMOS
LVPECL
LVDS/
CMOS
LVDS/
CMOS
LVDS/
CMOS
LVDS/
CP
PLL
Ref
LVPE CL
LVPE CL
LVPE CL
CLK2
LVPE CL
CMOS
LVDS/
CMOS
LVDS/
CMOS
LVDS/
CMOS
LVDS/
CP
CLK2
Outputs
AD9510
Clock
Input 2
Clock
Loop
Filter
VCO
BPF
Outputs
Clock