SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 941

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

35.7.33
Name:
Address:
Access:
This register acts as a double buffer for the CV and CVM values. This prevents an unexpected comparison x match.
Only the first 16 bits (channel counter size) of field CV
• CVUPD: Comparison x Value Update
Define the comparison x value to be compared with the counter of the channel 0.
• CVMUPD: Comparison x Value Mode Update
0 = The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is
incrementing.
1 = The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is
decrementing.
Note:
CAUTION: to be taken into account, the write of the register PWM_CMPVUPDx must be followed by a write of the register
PWM_CMPMUPDx.
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
31
23
15
–
7
This bit is useless if the counter of the channel 0 is left aligned (CALG = 0 in
PWM Comparison x Value Update Register
PWM_CMPVUPDx
0x40020134 [0], 0x40020144 [1], 0x40020154 [2], 0x40020164 [3], 0x40020174 [4], 0x40020184 [5],
0x40020194 [6], 0x400201A4 [7]
Write-only
30
22
14
–
6
29
21
13
–
5
28
20
12
–
4
UPD
CVUPD
CVUPD
CVUPD
are significant.
27
19
11
–
3
“PWM Channel Mode Register” on page
26
18
10
–
2
SAM3S8/SD8
SAM3S8/SD8
25
17
–
9
1
CVMUPD
24
16
944)
8
0
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