SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 716

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

32.7.3.3
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
Asynchronous Receiver
If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver over-
samples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock,
depending on the OVER bit in the Mode Register (US_MR).
The receiver samples the RXD line. If the line is sampled during one half of a bit time to 0, a start
bit is detected and data, parity and stop bits are successively sampled on the bit rate clock.
If the oversampling is 16, (OVER to 0), a start is detected at the eighth sample to 0. Then, data
bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8
(OVER to 1), a start bit is detected at the fourth sample to 0. Then, data bits, parity bit and stop
bit are sampled on each 8 sampling clock cycle.
The number of data bits, first bit sent and parity mode are selected by the same fields and bits
as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization
mechanism only, the number of stop bits has no effect on the receiver as it considers only one
stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the
transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking
for a new start bit so that resynchronization can also be accomplished when the transmitter is
operating with one stop bit.
Figure 32-12
operates in asynchronous mode.
Figure 32-12. Asynchronous Start Detection
Clock (x16)
Baud Rate
Sampling
Sampling
Sampling
Clock
RXD
RXD
and
1
1
Figure 32-13
2
2
3
3
4
4
5
5
6
6
illustrate start detection and character reception when USART
7
Detection
7
Rejection
Start
Start
8
0
1
1
2
2
3
3
4
4
5
6
7
8
9 10 11 12 13 14 15 16
SAM3S8/SD8
SAM3S8/SD8
Sampling
D0
716
716