SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 903

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

35.6.5.6
35.6.5.7
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
Interrupts
Write Protect Registers
Depending on the interrupt mask in the PWM_IMR1 and PWM_IMR2 registers, an interrupt can
be generated at the end of the corresponding channel period (CHIDx in the PWM_ISR1 regis-
ter), after a fault event (FCHIDx in the PWM_ISR1 register), after a comparison match (CMPMx
in the PWM_ISR2 register), after a comparison update (CMPUx in the PWM_ISR2 register) or
according to the transfer mode of the synchronous channels (WRDY, ENDTX, TXBUFE and
UNRE in the PWM_ISR2 register).
If the interrupt is generated by the flags CHIDx or FCHIDx, the interrupt remains active until a
read operation in the PWM_ISR1 register occurs.
If the interrupt is generated by the flags WRDY or UNRE or CMPMx or CMPUx, the interrupt
remains active until a read operation in the PWM_ISR2 register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER1 and
PWM_IER2 registers. A channel interrupt is disabled by setting the corresponding bit in the
PWM_IDR1 and PWM_IDR2 registers.
To prevent any single software error that may corrupt PWM behavior, the registers listed below
can be write-protected by writing the field WPCMD in the
on page 937
There are two types of Write Protect:
Both types of Write Protect can be applied independently to a particular register group by means
of the WPCMD and WPRG fields in PWM_WPCR register. If at least one Write Protect is active,
• Register group 0:
• Register group 1:
• Register group 2:
• Register group 3:
• Register group 4:
• Register group 5:
• Write Protect SW, which can be enabled or disabled.
• Write Protect HW, which can just be enabled, only a hardware reset of the PWM controller
can disable it.
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“PWM Clock Register” on page 908
“PWM Disable Register” on page 910
“PWM Sync Channels Mode Register” on page 916
“PWM Channel Mode Register” on page 944
“PWM Stepper Motor Mode Register” on page 936
“PWM Channel Period Register” on page 948
“PWM Channel Period Update Register” on page 949
“PWM Channel Dead Time Register” on page 951
“PWM Channel Dead Time Update Register” on page 952
“PWM Fault Mode Register” on page 930
“PWM Fault Protection Value Register” on page 933
(PWM_WPCR). They are divided into 6 groups:
“PWM Write Protect Control Register”
SAM3S8/SD8
SAM3S8/SD8
903
903