SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 212

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

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SAM3S8/SD8
SAM3S8/SD8
The behavior is not architecturally defined, and does not have to be documented by individual
implementations. Used when there are a number of implementation options available and the
option chosen does not affect software compatibility.
Index register
In some load and store instruction descriptions, the value of this register is used as an offset to
be added to or subtracted from the base register value to form the address that is sent to mem-
ory. Some addressing modes optionally enable the index register value to be shifted prior to the
addition or subtraction.
See also
Instruction cycle count
The number of cycles that an instruction occupies the Execute stage of the pipeline.
Interrupt handler
A program that control of the processor is passed to when an interrupt occurs.
Interrupt vector
One of a number of fixed addresses in low memory, or in high memory if high vectors are config-
ured, that contains the first instruction of the corresponding interrupt handler.
Little-endian (LE)
Byte ordering scheme in which bytes of increasing significance in a data word are stored at
increasing addresses in memory.
See also
Little-endian memory
Memory in which:
a byte or halfword at a word-aligned address is the least significant byte or halfword within the
word at that address
a byte at a halfword-aligned address is the least significant byte within the halfword at that
address.
Load/store architecture
A processor architecture where data-processing operations only operate on register contents,
not directly on memory contents.
Memory Protection Unit (MPU)
Hardware that controls access permissions to blocks of memory. An MPU does not perform any
address translation.
Prefetching
In pipelined processors, the process of fetching instructions from memory to fill up the pipeline
before the preceding instructions have finished executing. Prefetching an instruction does not
mean that the instruction has to be executed.
Read
Reads are defined as memory operations that have the semantics of a load. Reads include the
Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP.
“Base register”
“Condition field”
,
“Endianness”
.
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12