SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 508

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

Figure 27-6. Input Debouncing Filter Timing
27.5.10
508
508
Divided Slow Clock
if PIO_IFSR = 0
if PIO_IFSR = 1
PIO_PDSR
PIO_PDSR
Pin Level
SAM3S8/SD8
SAM3S8/SD8
Input Edge/Level Interrupt
up to 2 cycles Tmck
The PIO Controller can be programmed to generate an interrupt when it detects an edge or a
level on an I/O line. The Input Edge/Level Interrupt is controlled by writing PIO_IER (Interrupt
Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and dis-
able the input change interrupt by setting and clearing the corresponding bit in PIO_IMR
(Interrupt Mask Register). As Input change detection is possible only by comparing two succes-
sive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input
Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an
input only, controlled by the PIO Controller or assigned to a peripheral function.
By default, the interrupt can be generated at any time an edge is detected on the input.
Some additional Interrupt modes can be enabled/disabled by writing in the PIO_AIMER (Addi-
tional Interrupt Modes Enable Register) and PIO_AIMDR (Additional Interrupt Modes Disable
Register). The current state of this selection can be read through the PIO_AIMMR (Additional
Interrupt Modes Mask Register)
These Additional Modes are:
In order to select an Additional Interrupt Mode:
• Rising Edge Detection
• Falling Edge Detection
• Low Level Detection
• High Level Detection
• The type of event detection (Edge or Level) must be selected by writing in the set of registers;
• The Polarity of the event detection (Rising/Falling Edge or High/Low Level) must be selected
PIO_ESR (Edge Select Register) and PIO_LSR (Level Select Register) which enable
respectively, the Edge and Level Detection. The current status of this selection is accessible
through the PIO_ELSR (Edge/Level Status Register).
by writing in the set of registers; PIO_FELLSR (Falling Edge /Low Level Select Register) and
PIO_REHLSR (Rising Edge/High Level Select Register) which allow to select Falling or
Rising Edge (if Edge is selected in the PIO_ELSR) Edge or High or Low Level Detection (if
up to 2 cycles Tmck
PIO_IFCSR = 1
up to 1.5 cycles Tdiv_slclk
1 cycle Tdiv_slclk
up to 2 cycles Tmck
up to 1.5 cycles Tdiv_slclk
1 cycle Tdiv_slclk
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
up to 2 cycles Tmck