SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 613

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SAM3SD8B

Manufacturer Part Number
SAM3SD8B
Description
Manufacturer
Atmel Corporation
Datasheets
Figure 29-16. TWI Write Operation with Single Data Byte and Internal Address
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
- Internal address size (IADRSZ)
- Device slave address (DADR)
Set the Master Mode register:
TWI_CR = MSEN + SVDIS
Write ==> bit MREAD = 0
TWI_THR = Data to send
Set the internal address
Set the Control register:
Write STOP command
- Transfer direction bit
TWI_IADR = address
Load transmit register
Read Status register
Read Status register
(Needed only once)
TWI_CR = STOP
Transfer finished
Yes
- Master enable
TXCOMP = 1?
Set TWI clock
TXRDY = 1?
Yes
BEGIN
No
No
SAM3S8/SD8
SAM3S8/SD8
613
613

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